Lines Matching +full:0 +full:xf01
37 #define HDA_CMD_VERB_MASK 0x000fffff
38 #define HDA_CMD_VERB_SHIFT 0
39 #define HDA_CMD_NID_MASK 0x0ff00000
41 #define HDA_CMD_CAD_MASK 0xf0000000
62 #define HDA_CMD_VERB_GET_PARAMETER 0xf00
69 #define HDA_CMD_VERB_GET_CONN_SELECT_CONTROL 0xf01
70 #define HDA_CMD_VERB_SET_CONN_SELECT_CONTROL 0x701
74 HDA_CMD_VERB_GET_CONN_SELECT_CONTROL, 0x0))
80 #define HDA_CMD_VERB_GET_CONN_LIST_ENTRY 0xf02
90 #define HDA_CMD_VERB_GET_PROCESSING_STATE 0xf03
91 #define HDA_CMD_VERB_SET_PROCESSING_STATE 0x703
95 HDA_CMD_VERB_GET_PROCESSING_STATE, 0x0))
100 #define HDA_CMD_GET_PROCESSING_STATE_STATE_OFF 0x00
101 #define HDA_CMD_GET_PROCESSING_STATE_STATE_ON 0x01
102 #define HDA_CMD_GET_PROCESSING_STATE_STATE_BENIGN 0x02
105 #define HDA_CMD_VERB_GET_COEFF_INDEX 0xd
106 #define HDA_CMD_VERB_SET_COEFF_INDEX 0x5
110 HDA_CMD_VERB_GET_COEFF_INDEX, 0x0))
116 #define HDA_CMD_VERB_GET_PROCESSING_COEFF 0xc
117 #define HDA_CMD_VERB_SET_PROCESSING_COEFF 0x4
121 HDA_CMD_VERB_GET_PROCESSING_COEFF, 0x0))
127 #define HDA_CMD_VERB_GET_AMP_GAIN_MUTE 0xb
128 #define HDA_CMD_VERB_SET_AMP_GAIN_MUTE 0x3
137 #define HDA_CMD_GET_AMP_GAIN_MUTE_INPUT 0x0000
138 #define HDA_CMD_GET_AMP_GAIN_MUTE_OUTPUT 0x8000
139 #define HDA_CMD_GET_AMP_GAIN_MUTE_RIGHT 0x0000
140 #define HDA_CMD_GET_AMP_GAIN_MUTE_LEFT 0x2000
142 #define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_MASK 0x00000008
144 #define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_MASK 0x00000007
145 #define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_SHIFT 0
154 #define HDA_CMD_SET_AMP_GAIN_MUTE_OUTPUT 0x8000
155 #define HDA_CMD_SET_AMP_GAIN_MUTE_INPUT 0x4000
156 #define HDA_CMD_SET_AMP_GAIN_MUTE_LEFT 0x2000
157 #define HDA_CMD_SET_AMP_GAIN_MUTE_RIGHT 0x1000
158 #define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_MASK 0x0f00
160 #define HDA_CMD_SET_AMP_GAIN_MUTE_MUTE 0x0080
161 #define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_MASK 0x0007
162 #define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_SHIFT 0
172 #define HDA_CMD_VERB_GET_CONV_FMT 0xa
173 #define HDA_CMD_VERB_SET_CONV_FMT 0x2
177 HDA_CMD_VERB_GET_CONV_FMT, 0x0))
183 #define HDA_CMD_VERB_GET_DIGITAL_CONV_FMT1 0xf0d
184 #define HDA_CMD_VERB_GET_DIGITAL_CONV_FMT2 0xf0e
185 #define HDA_CMD_VERB_SET_DIGITAL_CONV_FMT1 0x70d
186 #define HDA_CMD_VERB_SET_DIGITAL_CONV_FMT2 0x70e
190 HDA_CMD_VERB_GET_DIGITAL_CONV_FMT1, 0x0))
198 #define HDA_CMD_GET_DIGITAL_CONV_FMT_CC_MASK 0x7f00
200 #define HDA_CMD_GET_DIGITAL_CONV_FMT_L_MASK 0x0080
202 #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_MASK 0x0040
204 #define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_MASK 0x0020
206 #define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_MASK 0x0010
208 #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_MASK 0x0008
210 #define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_MASK 0x0004
212 #define HDA_CMD_GET_DIGITAL_CONV_FMT_V_MASK 0x0002
214 #define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_MASK 0x0001
215 #define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_SHIFT 0
245 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_L 0x80
246 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_PRO 0x40
247 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO 0x20
248 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_COPY 0x10
249 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_PRE 0x08
250 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_VCFG 0x04
251 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_V 0x02
252 #define HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN 0x01
255 #define HDA_CMD_VERB_GET_POWER_STATE 0xf05
256 #define HDA_CMD_VERB_SET_POWER_STATE 0x705
260 HDA_CMD_VERB_GET_POWER_STATE, 0x0))
265 #define HDA_CMD_POWER_STATE_D0 0x00
266 #define HDA_CMD_POWER_STATE_D1 0x01
267 #define HDA_CMD_POWER_STATE_D2 0x02
268 #define HDA_CMD_POWER_STATE_D3 0x03
270 #define HDA_CMD_POWER_STATE_ACT_MASK 0x000000f0
272 #define HDA_CMD_POWER_STATE_SET_MASK 0x0000000f
273 #define HDA_CMD_POWER_STATE_SET_SHIFT 0
290 #define HDA_CMD_VERB_GET_CONV_STREAM_CHAN 0xf06
291 #define HDA_CMD_VERB_SET_CONV_STREAM_CHAN 0x706
295 HDA_CMD_VERB_GET_CONV_STREAM_CHAN, 0x0))
300 #define HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK 0x000000f0
302 #define HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK 0x0000000f
303 #define HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT 0
320 #define HDA_CMD_VERB_GET_INPUT_CONVERTER_SDI_SELECT 0xf04
321 #define HDA_CMD_VERB_SET_INPUT_CONVERTER_SDI_SELECT 0x704
325 HDA_CMD_VERB_GET_INPUT_CONVERTER_SDI_SELECT, 0x0))
331 #define HDA_CMD_VERB_GET_PIN_WIDGET_CTRL 0xf07
332 #define HDA_CMD_VERB_SET_PIN_WIDGET_CTRL 0x707
336 HDA_CMD_VERB_GET_PIN_WIDGET_CTRL, 0x0))
341 #define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_MASK 0x00000080
343 #define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_MASK 0x00000040
345 #define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_MASK 0x00000020
347 #define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK 0x00000007
348 #define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT 0
363 #define HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE 0x80
364 #define HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE 0x40
365 #define HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE 0x20
366 #define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK 0x07
367 #define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT 0
373 #define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_HIZ 0
380 #define HDA_CMD_VERB_GET_UNSOLICITED_RESPONSE 0xf08
381 #define HDA_CMD_VERB_SET_UNSOLICITED_RESPONSE 0x708
385 HDA_CMD_VERB_GET_UNSOLICITED_RESPONSE, 0x0))
390 #define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_MASK 0x00000080
392 #define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_MASK 0x0000001f
393 #define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_SHIFT 0
402 #define HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE 0x80
403 #define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_MASK 0x3f
404 #define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_SHIFT 0
411 #define HDA_CMD_VERB_GET_PIN_SENSE 0xf09
412 #define HDA_CMD_VERB_SET_PIN_SENSE 0x709
416 HDA_CMD_VERB_GET_PIN_SENSE, 0x0))
421 #define HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT 0x80000000
422 #define HDA_CMD_GET_PIN_SENSE_ELD_VALID 0x40000000
423 #define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_MASK 0x7fffffff
424 #define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_SHIFT 0
430 #define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_INVALID 0x7fffffff
432 #define HDA_CMD_SET_PIN_SENSE_LEFT_CHANNEL 0x00
433 #define HDA_CMD_SET_PIN_SENSE_RIGHT_CHANNEL 0x01
436 #define HDA_CMD_VERB_GET_EAPD_BTL_ENABLE 0xf0c
437 #define HDA_CMD_VERB_SET_EAPD_BTL_ENABLE 0x70c
441 HDA_CMD_VERB_GET_EAPD_BTL_ENABLE, 0x0))
446 #define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_MASK 0x00000004
448 #define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_MASK 0x00000002
450 #define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_MASK 0x00000001
451 #define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_SHIFT 0
463 #define HDA_CMD_SET_EAPD_BTL_ENABLE_LR_SWAP 0x04
464 #define HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD 0x02
465 #define HDA_CMD_SET_EAPD_BTL_ENABLE_BTL 0x01
468 #define HDA_CMD_VERB_GET_GPI_DATA 0xf10
469 #define HDA_CMD_VERB_SET_GPI_DATA 0x710
473 HDA_CMD_VERB_GET_GPI_DATA, 0x0))
479 #define HDA_CMD_VERB_GET_GPI_WAKE_ENABLE_MASK 0xf11
480 #define HDA_CMD_VERB_SET_GPI_WAKE_ENABLE_MASK 0x711
484 HDA_CMD_VERB_GET_GPI_WAKE_ENABLE_MASK, 0x0))
490 #define HDA_CMD_VERB_GET_GPI_UNSOLICITED_ENABLE_MASK 0xf12
491 #define HDA_CMD_VERB_SET_GPI_UNSOLICITED_ENABLE_MASK 0x712
495 HDA_CMD_VERB_GET_GPI_UNSOLICITED_ENABLE_MASK, 0x0))
501 #define HDA_CMD_VERB_GET_GPI_STICKY_MASK 0xf13
502 #define HDA_CMD_VERB_SET_GPI_STICKY_MASK 0x713
506 HDA_CMD_VERB_GET_GPI_STICKY_MASK, 0x0))
512 #define HDA_CMD_VERB_GET_GPO_DATA 0xf14
513 #define HDA_CMD_VERB_SET_GPO_DATA 0x714
517 HDA_CMD_VERB_GET_GPO_DATA, 0x0))
523 #define HDA_CMD_VERB_GET_GPIO_DATA 0xf15
524 #define HDA_CMD_VERB_SET_GPIO_DATA 0x715
528 HDA_CMD_VERB_GET_GPIO_DATA, 0x0))
534 #define HDA_CMD_VERB_GET_GPIO_ENABLE_MASK 0xf16
535 #define HDA_CMD_VERB_SET_GPIO_ENABLE_MASK 0x716
539 HDA_CMD_VERB_GET_GPIO_ENABLE_MASK, 0x0))
545 #define HDA_CMD_VERB_GET_GPIO_DIRECTION 0xf17
546 #define HDA_CMD_VERB_SET_GPIO_DIRECTION 0x717
550 HDA_CMD_VERB_GET_GPIO_DIRECTION, 0x0))
556 #define HDA_CMD_VERB_GET_GPIO_WAKE_ENABLE_MASK 0xf18
557 #define HDA_CMD_VERB_SET_GPIO_WAKE_ENABLE_MASK 0x718
561 HDA_CMD_VERB_GET_GPIO_WAKE_ENABLE_MASK, 0x0))
567 #define HDA_CMD_VERB_GET_GPIO_UNSOLICITED_ENABLE_MASK 0xf19
568 #define HDA_CMD_VERB_SET_GPIO_UNSOLICITED_ENABLE_MASK 0x719
572 HDA_CMD_VERB_GET_GPIO_UNSOLICITED_ENABLE_MASK, 0x0))
578 #define HDA_CMD_VERB_GET_GPIO_STICKY_MASK 0xf1a
579 #define HDA_CMD_VERB_SET_GPIO_STICKY_MASK 0x71a
583 HDA_CMD_VERB_GET_GPIO_STICKY_MASK, 0x0))
589 #define HDA_CMD_VERB_GET_BEEP_GENERATION 0xf0a
590 #define HDA_CMD_VERB_SET_BEEP_GENERATION 0x70a
594 HDA_CMD_VERB_GET_BEEP_GENERATION, 0x0))
600 #define HDA_CMD_VERB_GET_VOLUME_KNOB 0xf0f
601 #define HDA_CMD_VERB_SET_VOLUME_KNOB 0x70f
605 HDA_CMD_VERB_GET_VOLUME_KNOB, 0x0))
611 #define HDA_CMD_VERB_GET_SUBSYSTEM_ID 0xf20
612 #define HDA_CMD_VERB_SET_SUSBYSTEM_ID1 0x720
613 #define HDA_CMD_VERB_SET_SUBSYSTEM_ID2 0x721
614 #define HDA_CMD_VERB_SET_SUBSYSTEM_ID3 0x722
615 #define HDA_CMD_VERB_SET_SUBSYSTEM_ID4 0x723
619 HDA_CMD_VERB_GET_SUBSYSTEM_ID, 0x0))
634 #define HDA_CMD_VERB_GET_CONFIGURATION_DEFAULT 0xf1c
635 #define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT1 0x71c
636 #define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT2 0x71d
637 #define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT3 0x71e
638 #define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT4 0x71f
642 HDA_CMD_VERB_GET_CONFIGURATION_DEFAULT, 0x0))
657 #define HDA_CMD_VERB_GET_STRIPE_CONTROL 0xf24
658 #define HDA_CMD_VERB_SET_STRIPE_CONTROL 0x724
662 HDA_CMD_VERB_GET_STRIPE_CONTROL, 0x0))
668 #define HDA_CMD_VERB_GET_CONV_CHAN_COUNT 0xf2d
669 #define HDA_CMD_VERB_SET_CONV_CHAN_COUNT 0x72d
673 HDA_CMD_VERB_GET_CONV_CHAN_COUNT, 0x0))
678 #define HDA_CMD_VERB_GET_HDMI_DIP_SIZE 0xf2e
684 #define HDA_CMD_VERB_GET_HDMI_ELDD 0xf2f
690 #define HDA_CMD_VERB_GET_HDMI_DIP_INDEX 0xf30
691 #define HDA_CMD_VERB_SET_HDMI_DIP_INDEX 0x730
695 HDA_CMD_VERB_GET_HDMI_DIP_INDEX, 0x0))
700 #define HDA_CMD_VERB_GET_HDMI_DIP_DATA 0xf31
701 #define HDA_CMD_VERB_SET_HDMI_DIP_DATA 0x731
705 HDA_CMD_VERB_GET_HDMI_DIP_DATA, 0x0))
710 #define HDA_CMD_VERB_GET_HDMI_DIP_XMIT 0xf32
711 #define HDA_CMD_VERB_SET_HDMI_DIP_XMIT 0x732
715 HDA_CMD_VERB_GET_HDMI_DIP_XMIT, 0x0))
720 #define HDA_CMD_VERB_GET_HDMI_CP_CTRL 0xf33
721 #define HDA_CMD_VERB_SET_HDMI_CP_CTRL 0x733
723 #define HDA_CMD_VERB_GET_HDMI_CHAN_SLOT 0xf34
724 #define HDA_CMD_VERB_SET_HDMI_CHAN_SLOT 0x734
728 HDA_CMD_VERB_GET_HDMI_CHAN_SLOT, 0x0))
733 #define HDA_HDMI_CODING_TYPE_REF_STREAM_HEADER 0
751 #define HDA_CMD_VERB_FUNCTION_RESET 0x7ff
755 HDA_CMD_VERB_FUNCTION_RESET, 0x0))
762 #define HDA_PARAM_VENDOR_ID 0x00
764 #define HDA_PARAM_VENDOR_ID_VENDOR_ID_MASK 0xffff0000
766 #define HDA_PARAM_VENDOR_ID_DEVICE_ID_MASK 0x0000ffff
767 #define HDA_PARAM_VENDOR_ID_DEVICE_ID_SHIFT 0
777 #define HDA_PARAM_REVISION_ID 0x02
779 #define HDA_PARAM_REVISION_ID_MAJREV_MASK 0x00f00000
781 #define HDA_PARAM_REVISION_ID_MINREV_MASK 0x000f0000
783 #define HDA_PARAM_REVISION_ID_REVISION_ID_MASK 0x0000ff00
785 #define HDA_PARAM_REVISION_ID_STEPPING_ID_MASK 0x000000ff
786 #define HDA_PARAM_REVISION_ID_STEPPING_ID_SHIFT 0
802 #define HDA_PARAM_SUB_NODE_COUNT 0x04
804 #define HDA_PARAM_SUB_NODE_COUNT_START_MASK 0x00ff0000
806 #define HDA_PARAM_SUB_NODE_COUNT_TOTAL_MASK 0x000000ff
807 #define HDA_PARAM_SUB_NODE_COUNT_TOTAL_SHIFT 0
817 #define HDA_PARAM_FCT_GRP_TYPE 0x05
819 #define HDA_PARAM_FCT_GRP_TYPE_UNSOL_MASK 0x00000100
821 #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MASK 0x000000ff
822 #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_SHIFT 0
831 #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO 0x01
832 #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM 0x02
835 #define HDA_PARAM_AUDIO_FCT_GRP_CAP 0x08
837 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_MASK 0x00010000
839 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_MASK 0x00000f00
841 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_MASK 0x0000000f
842 #define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_SHIFT 0
855 #define HDA_PARAM_AUDIO_WIDGET_CAP 0x09
857 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK 0x00f00000
859 #define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_MASK 0x000f0000
861 #define HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_MASK 0x0000e000
863 #define HDA_PARAM_AUDIO_WIDGET_CAP_CP_MASK 0x00001000
865 #define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_MASK 0x00000800
867 #define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_MASK 0x00000400
869 #define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_MASK 0x00000200
871 #define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_MASK 0x00000100
873 #define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_MASK 0x00000080
875 #define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_MASK 0x00000040
877 #define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_MASK 0x00000020
879 #define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_MASK 0x00000010
881 #define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_MASK 0x00000008
883 #define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_MASK 0x00000004
885 #define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_MASK 0x00000002
887 #define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK 0x00000001
888 #define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT 0
941 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT 0x0
942 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT 0x1
943 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 0x2
944 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR 0x3
945 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX 0x4
946 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET 0x5
947 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET 0x6
948 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET 0x7
949 #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET 0xf
953 #define HDA_PARAM_SUPP_PCM_SIZE_RATE 0x0a
955 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_MASK 0x00100000
957 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_MASK 0x00080000
959 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_MASK 0x00040000
961 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_MASK 0x00020000
963 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_MASK 0x00010000
965 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_MASK 0x00000001
966 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_SHIFT 0
967 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_MASK 0x00000002
969 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_MASK 0x00000004
971 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_MASK 0x00000008
973 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_MASK 0x00000010
975 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_MASK 0x00000020
977 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_MASK 0x00000040
979 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_MASK 0x00000080
981 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_MASK 0x00000100
983 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_MASK 0x00000200
985 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_MASK 0x00000400
987 #define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_MASK 0x00000800
1043 #define HDA_PARAM_SUPP_STREAM_FORMATS 0x0b
1045 #define HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK 0x00000004
1047 #define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_MASK 0x00000002
1049 #define HDA_PARAM_SUPP_STREAM_FORMATS_PCM_MASK 0x00000001
1050 #define HDA_PARAM_SUPP_STREAM_FORMATS_PCM_SHIFT 0
1063 #define HDA_PARAM_PIN_CAP 0x0c
1065 #define HDA_PARAM_PIN_CAP_HBR_MASK 0x08000000
1067 #define HDA_PARAM_PIN_CAP_DP_MASK 0x01000000
1069 #define HDA_PARAM_PIN_CAP_EAPD_CAP_MASK 0x00010000
1071 #define HDA_PARAM_PIN_CAP_VREF_CTRL_MASK 0x0000ff00
1073 #define HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK 0x00002000
1075 #define HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK 0x00001000
1077 #define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_MASK 0x00000400
1079 #define HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK 0x00000200
1081 #define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_MASK 0x00000100
1083 #define HDA_PARAM_PIN_CAP_HDMI_MASK 0x00000080
1085 #define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_MASK 0x00000040
1087 #define HDA_PARAM_PIN_CAP_INPUT_CAP_MASK 0x00000020
1089 #define HDA_PARAM_PIN_CAP_OUTPUT_CAP_MASK 0x00000010
1091 #define HDA_PARAM_PIN_CAP_HEADPHONE_CAP_MASK 0x00000008
1093 #define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_MASK 0x00000004
1095 #define HDA_PARAM_PIN_CAP_TRIGGER_REQD_MASK 0x00000002
1097 #define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_MASK 0x00000001
1098 #define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_SHIFT 0
1153 #define HDA_PARAM_INPUT_AMP_CAP 0x0d
1155 #define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_MASK 0x80000000
1157 #define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_MASK 0x007f0000
1159 #define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_MASK 0x00007f00
1161 #define HDA_PARAM_INPUT_AMP_CAP_OFFSET_MASK 0x0000007f
1162 #define HDA_PARAM_INPUT_AMP_CAP_OFFSET_SHIFT 0
1178 #define HDA_PARAM_OUTPUT_AMP_CAP 0x12
1180 #define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_MASK 0x80000000
1182 #define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_MASK 0x007f0000
1184 #define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_MASK 0x00007f00
1186 #define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_MASK 0x0000007f
1187 #define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT 0
1203 #define HDA_PARAM_CONN_LIST_LENGTH 0x0e
1205 #define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_MASK 0x00000080
1207 #define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_MASK 0x0000007f
1208 #define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_SHIFT 0
1218 #define HDA_PARAM_SUPP_POWER_STATES 0x0f
1220 #define HDA_PARAM_SUPP_POWER_STATES_D3_MASK 0x00000008
1222 #define HDA_PARAM_SUPP_POWER_STATES_D2_MASK 0x00000004
1224 #define HDA_PARAM_SUPP_POWER_STATES_D1_MASK 0x00000002
1226 #define HDA_PARAM_SUPP_POWER_STATES_D0_MASK 0x00000001
1227 #define HDA_PARAM_SUPP_POWER_STATES_D0_SHIFT 0
1243 #define HDA_PARAM_PROCESSING_CAP 0x10
1245 #define HDA_PARAM_PROCESSING_CAP_NUMCOEFF_MASK 0x0000ff00
1247 #define HDA_PARAM_PROCESSING_CAP_BENIGN_MASK 0x00000001
1248 #define HDA_PARAM_PROCESSING_CAP_BENIGN_SHIFT 0
1258 #define HDA_PARAM_GPIO_COUNT 0x11
1260 #define HDA_PARAM_GPIO_COUNT_GPI_WAKE_MASK 0x80000000
1262 #define HDA_PARAM_GPIO_COUNT_GPI_UNSOL_MASK 0x40000000
1264 #define HDA_PARAM_GPIO_COUNT_NUM_GPI_MASK 0x00ff0000
1266 #define HDA_PARAM_GPIO_COUNT_NUM_GPO_MASK 0x0000ff00
1268 #define HDA_PARAM_GPIO_COUNT_NUM_GPIO_MASK 0x000000ff
1269 #define HDA_PARAM_GPIO_COUNT_NUM_GPIO_SHIFT 0
1288 #define HDA_PARAM_VOLUME_KNOB_CAP 0x13
1290 #define HDA_PARAM_VOLUME_KNOB_CAP_DELTA_MASK 0x00000080
1292 #define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_MASK 0x0000007f
1293 #define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_SHIFT 0
1302 #define HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK 0x0000000f
1303 #define HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT 0
1304 #define HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK 0x000000f0
1306 #define HDA_CONFIG_DEFAULTCONF_MISC_MASK 0x00000f00
1308 #define HDA_CONFIG_DEFAULTCONF_COLOR_MASK 0x0000f000
1310 #define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK 0x000f0000
1312 #define HDA_CONFIG_DEFAULTCONF_DEVICE_MASK 0x00f00000
1314 #define HDA_CONFIG_DEFAULTCONF_LOCATION_MASK 0x3f000000
1316 #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK 0xc0000000
1344 #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK (0<<30)
1349 #define HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT (0<<20)