Lines Matching +full:0 +full:x3e0
33 #define PCIV_ENVY24 0x1412
34 #define PCID_ENVY24HT 0x1724
36 #define PCIR_CCS 0x10 /* Controller I/O Base Address */
37 #define ENVY24HT_PCIR_MT 0x14 /* Multi-Track I/O Base Address */
41 #define ENVY24HT_CCS_CTL 0x00 /* Control/Status Register */
42 #define ENVY24HT_CCS_CTL_RESET 0x80 /* Entire Chip soft reset */
44 #define ENVY24HT_CCS_IMASK 0x01 /* Interrupt Mask Register */
45 #define ENVY24HT_CCS_IMASK_PMT 0x10 /* Professional Multi-track */
47 #define ENVY24HT_CCS_I2CDEV 0x10 /* I2C Port Device Address Register */
48 #define ENVY24HT_CCS_I2CDEV_ADDR 0xfe /* I2C device address */
49 #define ENVY24HT_CCS_I2CDEV_ROM 0xa0 /* reserved for the external I2C E2PROM */
50 #define ENVY24HT_CCS_I2CDEV_WR 0x01 /* write */
51 #define ENVY24HT_CCS_I2CDEV_RD 0x00 /* read */
53 #define ENVY24HT_CCS_I2CADDR 0x11 /* I2C Port Byte Address Register */
54 #define ENVY24HT_CCS_I2CDATA 0x12 /* I2C Port Read/Write Data Register */
56 #define ENVY24HT_CCS_I2CSTAT 0x13 /* I2C Port Control and Status Register */
57 #define ENVY24HT_CCS_I2CSTAT_ROM 0x80 /* external E2PROM exists */
58 #define ENVY24HT_CCS_I2CSTAT_BSY 0x01 /* I2C port read/write status busy */
60 #define ENVY24HT_CCS_SCFG 0x04 /* System Configuration Register */
61 #define ENVY24HT_CCSM_SCFG_XIN2 0xc0 /* XIN2 Clock Source Configuration */
65 #define ENVY24HT_CCSM_SCFG_MPU 0x20 /* 0(not implemented)/1(1) MPU-401 UART */
66 #define ENVY24HT_CCSM_SCFG_ADC 0x0c /* 1-2 stereo ADC connected, S/PDIF receiver connected */
67 #define ENVY24HT_CCSM_SCFG_DAC 0x03 /* 1-4 stereo DAC connected */
69 #define ENVY24HT_CCS_ACL 0x05 /* AC-Link Configuration Register */
70 #define ENVY24HT_CCSM_ACL_MTC 0x80 /* Multi-track converter type: 0:AC'97 1:I2S */
71 #define ENVY24HT_CCSM_ACL_OMODE 0x02 /* AC 97 codec SDATA_OUT 0:split 1:packed */
73 #define ENVY24HT_CCS_I2S 0x06 /* I2S Converters Features Register */
74 #define ENVY24HT_CCSM_I2S_VOL 0x80 /* I2S codec Volume and mute */
75 #define ENVY24HT_CCSM_I2S_96KHZ 0x40 /* I2S converter 96kHz sampling rate support */
76 #define ENVY24HT_CCSM_I2S_192KHZ 0x08 /* I2S converter 192kHz sampling rate support */
77 #define ENVY24HT_CCSM_I2S_RES 0x30 /* Converter resolution */
78 #define ENVY24HT_CCSM_I2S_16BIT 0x00 /* 16bit */
79 #define ENVY24HT_CCSM_I2S_18BIT 0x10 /* 18bit */
80 #define ENVY24HT_CCSM_I2S_20BIT 0x20 /* 20bit */
81 #define ENVY24HT_CCSM_I2S_24BIT 0x30 /* 24bit */
82 #define ENVY24HT_CCSM_I2S_ID 0x07 /* Other I2S IDs */
84 #define ENVY24HT_CCS_SPDIF 0x07 /* S/PDIF Configuration Register */
85 #define ENVY24HT_CCSM_SPDIF_INT_EN 0x80 /* Enable integrated S/PDIF transmitter */
86 #define ENVY24HT_CCSM_SPDIF_INT_OUT 0x40 /* Internal S/PDIF Out implemented */
87 #define ENVY24HT_CCSM_SPDIF_ID 0x3c /* S/PDIF chip ID */
88 #define ENVY24HT_CCSM_SPDIF_IN 0x02 /* S/PDIF Stereo In is present */
89 #define ENVY24HT_CCSM_SPDIF_OUT 0x01 /* External S/PDIF Out implemented */
93 #define ENVY24HT_MT_INT_STAT 0x00 /* DMA Interrupt Mask and Status Register */
94 #define ENVY24HT_MT_INT_RSTAT 0x02 /* Multi-track record interrupt status */
95 #define ENVY24HT_MT_INT_PSTAT 0x01 /* Multi-track playback interrupt status */
96 #define ENVY24HT_MT_INT_MASK 0x03
97 #define ENVY24HT_MT_INT_RMASK 0x02 /* Multi-track record interrupt mask */
98 #define ENVY24HT_MT_INT_PMASK 0x01 /* Multi-track playback interrupt mask */
100 #define ENVY24HT_MT_RATE 0x01 /* Sampling Rate Select Register */
101 #define ENVY24HT_MT_RATE_SPDIF 0x10 /* S/PDIF input clock as the master */
102 #define ENVY24HT_MT_RATE_48000 0x00
103 #define ENVY24HT_MT_RATE_24000 0x01
104 #define ENVY24HT_MT_RATE_12000 0x02
105 #define ENVY24HT_MT_RATE_9600 0x03
106 #define ENVY24HT_MT_RATE_32000 0x04
107 #define ENVY24HT_MT_RATE_16000 0x05
108 #define ENVY24HT_MT_RATE_8000 0x06
109 #define ENVY24HT_MT_RATE_96000 0x07
110 #define ENVY24HT_MT_RATE_192000 0x0e
111 #define ENVY24HT_MT_RATE_64000 0x0f
112 #define ENVY24HT_MT_RATE_44100 0x08
113 #define ENVY24HT_MT_RATE_22050 0x09
114 #define ENVY24HT_MT_RATE_11025 0x0a
115 #define ENVY24HT_MT_RATE_88200 0x0b
116 #define ENVY24HT_MT_RATE_176400 0x0c
117 #define ENVY24HT_MT_RATE_MASK 0x0f
119 #define ENVY24HT_MT_I2S 0x02 /* I2S Data Format Register */
120 #define ENVY24HT_MT_I2S_MLR128 0x08 /* MCLK/LRCLK ratio 128x (or 256x) */
122 #define ENVY24HT_MT_PADDR 0x10 /* Playback DMA Current/Base Address Register */
123 #define ENVY24HT_MT_PCNT 0x14 /* Playback DMA Current/Base Count Register */
124 #define ENVY24HT_MT_PTERM 0x1C /* Playback Current/Base Terminal Count Register */
126 #define ENVY24HT_MT_PCTL 0x18 /* Global Playback and Record DMA Start/Stop Register */
127 #define ENVY24HT_MT_PCTL_RSTART 0x02 /* 1: Record start; 0: Record stop */
128 #define ENVY24HT_MT_PCTL_PSTART 0x01 /* 1: Playback start; 0: Playback stop */
130 #define ENVY24HT_MT_RADDR 0x20 /* Record DMA Current/Base Address Register */
131 #define ENVY24HT_MT_RCNT 0x24 /* Record DMA Current/Base Count Register */
132 #define ENVY24HT_MT_RTERM 0x26 /* Record Current/Base Terminal Count Register */
138 #define ENVY24HT_E2PROM_SUBVENDOR 0x02
139 #define ENVY24HT_E2PROM_SUBDEVICE 0x00
140 #define ENVY24HT_E2PROM_SIZE 0x04
141 #define ENVY24HT_E2PROM_VERSION 0x05
142 #define ENVY24HT_E2PROM_SCFG 0x06
143 #define ENVY24HT_E2PROM_ACL 0x07
144 #define ENVY24HT_E2PROM_I2S 0x08
145 #define ENVY24HT_E2PROM_SPDIF 0x09
146 #define ENVY24HT_E2PROM_GPIOMASK 0x0d
147 #define ENVY24HT_E2PROM_GPIOSTATE 0x10
148 #define ENVY24HT_E2PROM_GPIODIR 0x0a
158 #define ENVY24HT_CHAN_PLAY_DAC1 0
170 #define ENVY24HT_MIX_MASK 0x3fd
171 #define ENVY24HT_MIX_REC_MASK 0x3e0
174 #define ENVY24HT_VOL_MAX 0 /* 0db(negate) */
178 #define BUS_SPACE_MAXSIZE_ENVY24 0x3fffc /* 64k x 4byte(1dword) */
180 #define ENVY24HT_CCS_GPIO_HDATA 0x1E
181 #define ENVY24HT_CCS_GPIO_LDATA 0x14
182 #define ENVY24HT_CCS_GPIO_LMASK 0x16
183 #define ENVY24HT_CCS_GPIO_HMASK 0x1F
184 #define ENVY24HT_CCS_GPIO_CTLDIR 0x18