Lines Matching +full:dma +full:- +full:channel +full:- +full:mask
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 /* -------------------------------------------------------------------- */
39 #define PCIR_DS 0x18 /* DMA Path Registers I/O Base Address */
40 #define PCIR_MT 0x1c /* Professional Multi-Track I/O Base Address */
44 #define PCIM_LAC_SBDMA0 0x0000 /* SB DMA Channel Select: 0 */
45 #define PCIM_LAC_SBDMA1 0x0040 /* SB DMA Channel Select: 1 */
46 #define PCIM_LAC_SBDMA3 0x00c0 /* SB DMA Channel Select: 3 */
48 #define PCIM_LAC_MPU401 0x0008 /* MPU-401 I/O enable */
60 #define PCIM_LCC_MPUBASE 0x0006 /* MPU-401 base 300h-330h */
61 #define PCIM_LCC_LDMA 0x0001 /* Legacy DMA enable */
68 #define PCIM_SCFG_MPU 0x20 /* 1(0)/2(1) MPU-401 UART(s) */
71 #define PCIM_SCFG_ADC 0x0c /* 1-4 stereo ADC connected */
72 #define PCIM_SCFG_DAC 0x03 /* 1-4 stereo DAC connected */
74 #define PCIR_ACL 0x61 /* AC-Link Configuration Register */
75 #define PCIM_ACL_MTC 0x80 /* Multi-track converter type: 0:AC'97 1:I2S */
100 #define ENVY24_CCS_CTL_DMAINT 0x40 /* DS DMA Channel-C interrupt */
106 #define ENVY24_CCS_IMASK 0x01 /* Interrupt Mask Register */
110 #define ENVY24_CCS_IMASK_PMT 0x10 /* Professional Multi-track */
112 #define ENVY24_CCS_IMASK_PDMA 0x04 /* Playback DS DMA */
113 #define ENVY24_CCS_IMASK_RDMA 0x02 /* Consumer record DMA */
120 #define ENVY24_CCS_ISTAT_PMT 0x10 /* Professional Multi-track */
122 #define ENVY24_CCS_ISTAT_PDMA 0x04 /* Playback DS DMA */
123 #define ENVY24_CCS_ISTAT_RDMA 0x02 /* Consumer record DMA */
132 #define ENVY24_CCS_NMI1_SBDMA 0x10 /* SB interrupt (SB DMA/SB F2 command) */
133 #define ENVY24_CCS_NMI1_DSDMA 0x08 /* DS channel C DMA interrupt */
183 #define ENVY24_CCS_CDMABASE 0x14 /* Consumer Record DMA Current/Base Address Register */
184 #define ENVY24_CCS_CDMACNT 0x18 /* Consumer Record DMA Current/Base Count Register */
191 #define ENVY24_CCS_TIMER_MASK 0x7fff /* Timer counter mask */
210 #define ENVY24_CCI_VOL_MASK 0x3f /* Volume value mask */
228 #define ENVY24_CCI_GPIOMASK 0x21 /* GPIO Write Mask Register */
241 #define ENVY24_CCI_CPDWN_PCI 0x01 /* PCI clock for SB, DMA controller */
243 #define ENVY24_CCI_MTPDWN 0x31 /* Multi-Track Section Power Down Register */
247 #define ENVY24_CCI_MTPDWN_I2S 0x01 /* Multi-track I2S serial interface clock */
251 #define ENVY24_DDMA_ADDR0 0x00 /* DMA Base and Current Address bit 0-7 */
252 #define ENVY24_DDMA_ADDR8 0x01 /* DMA Base and Current Address bit 8-15 */
253 #define ENVY24_DDMA_ADDR16 0x02 /* DMA Base and Current Address bit 16-23 */
254 #define ENVY24_DDMA_ADDR24 0x03 /* DMA Base and Current Address bit 24-31 */
255 #define ENVY24_DDMA_CNT0 0x04 /* DMA Base and Current Count 0-7 */
256 #define ENVY24_DDMA_CNT8 0x05 /* DMA Base and Current Count 8-15 */
261 #define ENVY24_DDMA_CHAN 0x0f /* Channel Mask */
263 /* Consumer Section DMA Channel Registers */
265 #define ENVY24_CS_INTMASK 0x00 /* DirectSound DMA Interrupt Mask Register */
266 #define ENVY24_CS_INTSTAT 0x02 /* DirectSound DMA Interrupt Status Register */
267 #define ENVY24_CS_CHDAT 0x04 /* Channel Data register */
269 #define ENVY24_CS_CHIDX 0x08 /* Channel Index Register */
270 #define ENVY24_CS_CHIDX_NUM 0xf0 /* Channel number */
271 #define ENVY24_CS_CHIDX_ADDR0 0x00 /* Buffer_0 DMA base address */
272 #define ENVY24_CS_CHIDX_CNT0 0x01 /* Buffer_0 DMA base count */
273 #define ENVY24_CS_CHIDX_ADDR1 0x02 /* Buffer_1 DMA base address */
274 #define ENVY24_CS_CHIDX_CNT1 0x03 /* Buffer_1 DMA base count */
275 #define ENVY24_CS_CHIDX_CTL 0x04 /* Channel Control and Status register */
276 #define ENVY24_CS_CHIDX_RATE 0x05 /* Channel Sampling Rate */
277 #define ENVY24_CS_CHIDX_VOL 0x06 /* Channel left and right volume/pan control */
278 /* Channel Control and Status Register at Index 4h */
284 #define ENVY24_CS_CTL_U8 0x04 /* 8-bit unsigned(or 16-bit signed) */
285 #define ENVY24_CS_CTL_PAUSE 0x02 /* DMA request 1:pause */
286 #define ENVY24_CS_CTL_START 0x01 /* DMA request 1: start, 0:stop */
291 /* Professional Multi-Track Control Registers */
293 #define ENVY24_MT_INT 0x00 /* DMA Interrupt Mask and Status Register */
294 #define ENVY24_MT_INT_RMASK 0x80 /* Multi-track record interrupt mask */
295 #define ENVY24_MT_INT_PMASK 0x40 /* Multi-track playback interrupt mask */
296 #define ENVY24_MT_INT_RSTAT 0x02 /* Multi-track record interrupt status */
297 #define ENVY24_MT_INT_PSTAT 0x01 /* Multi-track playback interrupt status */
329 #define ENVY24_MT_AC97CMD_ID 0x03 /* ID(0-3) for external AC 97 registers */
333 #define ENVY24_MT_PADDR 0x10 /* Playback DMA Current/Base Address Register */
334 #define ENVY24_MT_PCNT 0x14 /* Playback DMA Current/Base Count Register */
341 #define ENVY24_MT_RADDR 0x20 /* Record DMA Current/Base Address Register */
342 #define ENVY24_MT_RCNT 0x24 /* Record DMA Current/Base Count Register */
355 #define ENVY24_MT_VOLUME_L 0x007f /* Left Volume Mask */
356 #define ENVY24_MT_VOLUME_R 0x7f00 /* Right Volume Mask */
364 /* -------------------------------------------------------------------- */
366 /* ENVY24 mixer channel defines */
391 #define ENVY24_VOL_MIN 96 /* -144db(negate) */
394 /* -------------------------------------------------------------------- */
398 ENVY24 has input->output data routing matrix switch. But original ENVY24
404 a. direct output from DMA
405 b. MIXER output which mixed the DMA outputs and input channels
406 (NOTICE: this class is able to set only DAC-1 and S/PDIF output)
409 3: input ADC channel selection(when 2:c. is selected)
437 /* -------------------------------------------------------------------- */
462 /* GPIO connect map of M-Audio Delta series */
472 /* M-Audio Delta series S/PDIF(CS84[01]4) control pin values */
478 /* M-Audio Delta series parameter */