Lines Matching +full:ac +full:- +full:power
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 /* -------------------------------------------------------------------- */
40 #define PCIR_MT 0x1c /* Professional Multi-Track I/O Base Address */
48 #define PCIM_LAC_MPU401 0x0008 /* MPU-401 I/O enable */
60 #define PCIM_LCC_MPUBASE 0x0006 /* MPU-401 base 300h-330h */
68 #define PCIM_SCFG_MPU 0x20 /* 1(0)/2(1) MPU-401 UART(s) */
69 #define PCIM_SCFG_AC97 0x10 /* 0: AC'97 codec exist */
70 /* 1: AC'97 codec not exist */
71 #define PCIM_SCFG_ADC 0x0c /* 1-4 stereo ADC connected */
72 #define PCIM_SCFG_DAC 0x03 /* 1-4 stereo DAC connected */
74 #define PCIR_ACL 0x61 /* AC-Link Configuration Register */
75 #define PCIM_ACL_MTC 0x80 /* Multi-track converter type: 0:AC'97 1:I2S */
76 #define PCIM_ACL_OMODE 0x02 /* AC 97 codec SDATA_OUT 0:split 1:packed */
77 #define PCIM_ACL_IMODE 0x01 /* AC 97 codec SDATA_IN 0:split 1:packed */
94 #define PCIR_POWER_STAT 0x84 /* Power Management Control and Status */
100 #define ENVY24_CCS_CTL_DMAINT 0x40 /* DS DMA Channel-C interrupt */
110 #define ENVY24_CCS_IMASK_PMT 0x10 /* Professional Multi-track */
120 #define ENVY24_CCS_ISTAT_PMT 0x10 /* Professional Multi-track */
139 #define ENVY24_CCS_AC97IDX 0x08 /* Consumer AC'97 Index Register */
141 #define ENVY24_CCS_AC97CMD 0x09 /* Consumer AC'97 Command/Status Register */
144 #define ENVY24_CCS_AC97CMD_WRCODEC 0x20 /* Write to AC'97 codec registers */
145 #define ENVY24_CCS_AC97CMD_RDCODEC 0x10 /* Read from AC'97 codec registers */
146 #define ENVY24_CCS_AC97CMD_READY 0x08 /* AC'97 codec ready status bit */
150 #define ENVY24_CCS_AC97DAT 0x0a /* Consumer AC'97 Data Port Register */
234 #define ENVY24_CCI_CPDWN 0x30 /* Consumer Section Power Down Register */
235 #define ENVY24_CCI_CPDWN_XTAL 0x80 /* Crystal clock generation power down for XTAL_1 */
236 #define ENVY24_CCI_CPDWN_GAME 0x40 /* Game port analog power down */
239 #define ENVY24_CCI_CPDWN_AC97 0x04 /* AC'97 clock */
243 #define ENVY24_CCI_MTPDWN 0x31 /* Multi-Track Section Power Down Register */
244 #define ENVY24_CCI_MTPDWN_XTAL 0x80 /* Crystal clock generation power down for XTAL_2 */
247 #define ENVY24_CCI_MTPDWN_I2S 0x01 /* Multi-track I2S serial interface clock */
251 #define ENVY24_DDMA_ADDR0 0x00 /* DMA Base and Current Address bit 0-7 */
252 #define ENVY24_DDMA_ADDR8 0x01 /* DMA Base and Current Address bit 8-15 */
253 #define ENVY24_DDMA_ADDR16 0x02 /* DMA Base and Current Address bit 16-23 */
254 #define ENVY24_DDMA_ADDR24 0x03 /* DMA Base and Current Address bit 24-31 */
255 #define ENVY24_DDMA_CNT0 0x04 /* DMA Base and Current Count 0-7 */
256 #define ENVY24_DDMA_CNT8 0x05 /* DMA Base and Current Count 8-15 */
284 #define ENVY24_CS_CTL_U8 0x04 /* 8-bit unsigned(or 16-bit signed) */
291 /* Professional Multi-Track Control Registers */
294 #define ENVY24_MT_INT_RMASK 0x80 /* Multi-track record interrupt mask */
295 #define ENVY24_MT_INT_PMASK 0x40 /* Multi-track playback interrupt mask */
296 #define ENVY24_MT_INT_RSTAT 0x02 /* Multi-track record interrupt status */
297 #define ENVY24_MT_INT_PSTAT 0x01 /* Multi-track playback interrupt status */
321 #define ENVY24_MT_AC97IDX 0x04 /* Index Register for AC'97 Codecs */
323 #define ENVY24_MT_AC97CMD 0x05 /* Command and Status Register for AC'97 Codecs */
326 #define ENVY24_MT_AC97CMD_WR 0x20 /* write to AC'97 codec register */
327 #define ENVY24_MT_AC97CMD_RD 0x10 /* read AC'97 CODEC register */
328 #define ENVY24_MT_AC97CMD_RDY 0x08 /* AC'97 codec ready status bit */
329 #define ENVY24_MT_AC97CMD_ID 0x03 /* ID(0-3) for external AC 97 registers */
331 #define ENVY24_MT_AC97DLO 0x06 /* AC'97 codec register data low byte */
332 #define ENVY24_MT_AC97DHI 0x07 /* AC'97 codec register data high byte */
364 /* -------------------------------------------------------------------- */
369 able to use for this. If system has consumer AC'97 output, AC'97 line is
391 #define ENVY24_VOL_MIN 96 /* -144db(negate) */
394 /* -------------------------------------------------------------------- */
398 ENVY24 has input->output data routing matrix switch. But original ENVY24
406 (NOTICE: this class is able to set only DAC-1 and S/PDIF output)
437 /* -------------------------------------------------------------------- */
462 /* GPIO connect map of M-Audio Delta series */
472 /* M-Audio Delta series S/PDIF(CS84[01]4) control pin values */
478 /* M-Audio Delta series parameter */