Lines Matching +full:0 +full:x1002
49 #define ATI_VENDOR_ID 0x1002 /* ATI Technologies */
51 #define ATI_IXP_200_ID 0x4341
52 #define ATI_IXP_300_ID 0x4361
53 #define ATI_IXP_400_ID 0x4370
54 #define ATI_IXP_SB600_ID 0x4382
66 #define ATI_REG_ISR 0x00 /* interrupt source */
67 #define ATI_REG_ISR_IN_XRUN (1U<<0)
80 #define ATI_REG_IER 0x04 /* interrupt enable */
81 #define ATI_REG_IER_IN_XRUN_EN (1U<<0)
95 #define ATI_REG_CMD 0x08 /* command */
96 #define ATI_REG_CMD_POWERDOWN (1U<<0)
127 #define ATI_REG_PHYS_OUT_ADDR 0x0c
128 #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
134 #define ATI_REG_PHYS_IN_ADDR 0x10
139 #define ATI_REG_SLOTREQ 0x14
141 #define ATI_REG_COUNTER 0x18
142 #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
145 #define ATI_REG_IN_FIFO_THRESHOLD 0x1c
147 #define ATI_REG_IN_DMA_LINKPTR 0x20
148 #define ATI_REG_IN_DMA_DT_START 0x24 /* RO */
149 #define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */
150 #define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */
151 #define ATI_REG_IN_DMA_DT_SIZE 0x30
153 #define ATI_REG_OUT_DMA_SLOT 0x34
155 #define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff
156 #define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800
159 #define ATI_REG_OUT_DMA_LINKPTR 0x38
160 #define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */
161 #define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */
162 #define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */
163 #define ATI_REG_OUT_DMA_DT_SIZE 0x48
165 #define ATI_REG_SPDF_CMD 0x4c
168 #define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */
170 #define ATI_REG_SPDF_DMA_LINKPTR 0x50
171 #define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */
172 #define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */
173 #define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */
174 #define ATI_REG_SPDF_DMA_DT_SIZE 0x60
176 #define ATI_REG_MODEM_MIRROR 0x7c
177 #define ATI_REG_AUDIO_MIRROR 0x80
179 #define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */
180 #define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
182 #define ATI_REG_FIFO_FLUSH 0x88
183 #define ATI_REG_FIFO_OUT_FLUSH (1U<<0)
187 #define ATI_REG_LINKPTR_EN (1U<<0)
190 #define ATI_REG_DMA_DT_SIZE (0xffffU<<0)
191 #define ATI_REG_DMA_FIFO_USED (0x1fU<<16)
192 #define ATI_REG_DMA_FIFO_FREE (0x1fU<<21)