137 #define atiixp_rd(_sc, _reg)	\  macro
226 	value = atiixp_rd(sc, ATI_REG_IER);  in atiixp_enable_interrupts()
264 	value = atiixp_rd(sc, ATI_REG_CMD);  in atiixp_reset_aclink()
275 	value  = atiixp_rd(sc, ATI_REG_CMD);  in atiixp_reset_aclink()
280 	value  = atiixp_rd(sc, ATI_REG_CMD);  in atiixp_reset_aclink()
284 	value  = atiixp_rd(sc, ATI_REG_CMD);  in atiixp_reset_aclink()
290 	value = atiixp_rd(sc, ATI_REG_CMD);  in atiixp_reset_aclink()
302 		value = atiixp_rd(sc, ATI_REG_CMD);  in atiixp_reset_aclink()
306 		value = atiixp_rd(sc, ATI_REG_CMD);  in atiixp_reset_aclink()
311 		value = atiixp_rd(sc, ATI_REG_CMD);  in atiixp_reset_aclink()
322 	value  = atiixp_rd(sc, ATI_REG_CMD);  in atiixp_reset_aclink()
338 	value = atiixp_rd(ch->parent, ATI_REG_CMD);  in atiixp_enable_dma()
350 	value = atiixp_rd(ch->parent, ATI_REG_CMD);  in atiixp_disable_dma()
366 		if ((atiixp_rd(sc, ATI_REG_PHYS_OUT_ADDR) &  in atiixp_waitready_codec()
395 		data = atiixp_rd(sc, ATI_REG_PHYS_IN_ADDR);  in atiixp_rdcd()
494 		value = atiixp_rd(sc, ATI_REG_CMD);  in atiixp_chan_setformat()
500 		value = atiixp_rd(sc, ATI_REG_OUT_DMA_SLOT);  in atiixp_chan_setformat()
507 		value = atiixp_rd(sc, ATI_REG_CMD);  in atiixp_chan_setformat()
512 		value = atiixp_rd(sc, ATI_REG_6CH_REORDER);  in atiixp_chan_setformat()
618 		ptr = atiixp_rd(sc, reg);  in atiixp_dmapos()
812 	value = atiixp_rd(sc, ATI_REG_IER);  in atiixp_chan_trigger()
813 	if (atiixp_rd(sc, ATI_REG_CMD) & (ATI_REG_CMD_SEND_EN |  in atiixp_chan_trigger()
880 	status = atiixp_rd(sc, ATI_REG_ISR);  in atiixp_intr()
911 		enable  = atiixp_rd(sc, ATI_REG_IER);  in atiixp_intr()
945 	value = atiixp_rd(sc, ATI_REG_CMD);  in atiixp_chip_pre_init()