1 /*-
2  * Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
37 	db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,  in sis_disable_msix()
40 	PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,  in sis_disable_msix()
42 	OS_SLEEP(1000);     /* 1 ms delay for PCI W/R ordering issue */  in sis_disable_msix()
54 	db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,  in sis_enable_intx()
57 	PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,  in sis_enable_intx()
59 	OS_SLEEP(1000);     /* 1 ms delay for PCI W/R ordering issue */  in sis_enable_intx()
74 	db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,  in sis_disable_intx()
77 	PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,  in sis_disable_intx()
79 	OS_SLEEP(1000);     /* 1 ms delay for PCI W/R ordering issue */  in sis_disable_intx()
89 	switch(softs->intr_type) {  in sis_disable_interrupt()
114 	PCI_MEM_PUT32(softs,  &softs->ioa_reg->host_to_ioa_db,  in pqisrc_trigger_nmi_sis()
124 	uint32_t timeout = SIS_ENABLE_TIMEOUT;  in pqisrc_reenable_sis()  local
128 	PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,  in pqisrc_reenable_sis()
130 	OS_SLEEP(1000);     /* 1 ms delay for PCI W/R ordering issue */  in pqisrc_reenable_sis()
132 	COND_WAIT(((PCI_MEM_GET32(softs, &softs->ioa_reg->ioa_to_host_db, LEGACY_SIS_ODBR_R) &  in pqisrc_reenable_sis()
133 				REENABLE_SIS) == 0), timeout)  in pqisrc_reenable_sis()
134 	if (!timeout) {  in pqisrc_reenable_sis()
148 	uint32_t timeout = SIS_STATUS_OK_TIMEOUT;  in pqisrc_check_fw_status()  local
154 		PQI_CTRL_KERNEL_UP_AND_RUNNING), timeout);  in pqisrc_check_fw_status()
155 	if (!timeout) {  in pqisrc_check_fw_status()
170 	uint32_t timeout = SIS_CMD_COMPLETE_TIMEOUT;  in pqisrc_send_sis_cmd()  local
179 		PCI_MEM_PUT32(softs, &softs->ioa_reg->mb[i],  in pqisrc_send_sis_cmd()
183 	PCI_MEM_PUT32(softs, &softs->ioa_reg->ioa_to_host_db_clr,  in pqisrc_send_sis_cmd()
187 	PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,  in pqisrc_send_sis_cmd()
195 	val = PCI_MEM_GET32(softs, &softs->ioa_reg->ioa_to_host_db, LEGACY_SIS_ODBR_R);  in pqisrc_send_sis_cmd()
199 	COND_WAIT((PCI_MEM_GET32(softs, &softs->ioa_reg->ioa_to_host_db, LEGACY_SIS_ODBR_R) &  in pqisrc_send_sis_cmd()
200 		SIS_CMD_COMPLETE), timeout);  in pqisrc_send_sis_cmd()
201 	if (!timeout) {  in pqisrc_send_sis_cmd()
207 	mb[0] = LE_32(PCI_MEM_GET32(softs, &softs->ioa_reg->mb[0], LEGACY_SIS_SRCV_MAILBOX));  in pqisrc_send_sis_cmd()
210 		DBG_ERR("SIS cmd failed with status = 0x%x\n",  in pqisrc_send_sis_cmd()
218 		mb[i] =	LE_32(PCI_MEM_GET32(softs, &softs->ioa_reg->mb[i], LEGACY_SIS_SRCV_MAILBOX+i*4));  in pqisrc_send_sis_cmd()
264 		softs->pref_settings.max_cmd_size = mb[1] >> 16;  in pqisrc_get_preferred_settings()
266 		softs->pref_settings.max_fib_size = mb[1] & 0x0000FFFF;  in pqisrc_get_preferred_settings()
267 		DBG_INIT("cmd size = %x, fib size = %x\n",  in pqisrc_get_preferred_settings()
268 			softs->pref_settings.max_cmd_size,  in pqisrc_get_preferred_settings()
269 			softs->pref_settings.max_fib_size);  in pqisrc_get_preferred_settings()
288 		softs->pqi_cap.max_sg_elem = mb[1];  in pqisrc_get_sis_pqi_cap()
289 		softs->pqi_cap.max_transfer_size = mb[2];  in pqisrc_get_sis_pqi_cap()
290 		softs->pqi_cap.max_outstanding_io = mb[3];  in pqisrc_get_sis_pqi_cap()
291 		if (softs->pqi_cap.max_outstanding_io >  in pqisrc_get_sis_pqi_cap()
293 			DBG_WARN("Controller-supported max outstanding "  in pqisrc_get_sis_pqi_cap()
295 				"driver-supported max.\n",  in pqisrc_get_sis_pqi_cap()
296 				softs->pqi_cap.max_outstanding_io,  in pqisrc_get_sis_pqi_cap()
298 			softs->pqi_cap.max_outstanding_io =  in pqisrc_get_sis_pqi_cap()
306 		softs->pqi_cap.conf_tab_off = mb[4];  in pqisrc_get_sis_pqi_cap()
307 		softs->pqi_cap.conf_tab_sz =  mb[5];  in pqisrc_get_sis_pqi_cap()
312 					softs->pqi_cap.max_sg_elem);  in pqisrc_get_sis_pqi_cap()
314 					softs->pqi_cap.max_transfer_size);  in pqisrc_get_sis_pqi_cap()
316 					softs->pqi_cap.max_outstanding_io);  in pqisrc_get_sis_pqi_cap()
318 					softs->pqi_cap.conf_tab_off);  in pqisrc_get_sis_pqi_cap()
320 					softs->pqi_cap.conf_tab_sz);  in pqisrc_get_sis_pqi_cap()
328 /* Send INIT STRUCT BASE ADDR - one of the SIS command */
354 	/* The valid tag values are from 1, 2, ..., softs->max_outstanding_io  in pqisrc_init_struct_base()
358 	num_elem = softs->pqi_cap.max_outstanding_io + 1;  in pqisrc_init_struct_base()
360 	softs->err_buf_dma_mem.size = num_elem * elem_size;  in pqisrc_init_struct_base()
363 	softs->err_buf_dma_mem.align = PQISRC_ERR_BUF_DMA_ALIGN;  in pqisrc_init_struct_base()
364 	os_strlcpy(softs->err_buf_dma_mem.tag, "error_buffer", sizeof(softs->err_buf_dma_mem.tag));  in pqisrc_init_struct_base()
365 	ret = os_dma_mem_alloc(softs, &softs->err_buf_dma_mem);  in pqisrc_init_struct_base()
374 	init_struct->revision = PQISRC_INIT_STRUCT_REVISION;  in pqisrc_init_struct_base()
375 	init_struct->flags    = 0;  in pqisrc_init_struct_base()
376 	init_struct->err_buf_paddr_l = DMA_PHYS_LOW(&softs->err_buf_dma_mem);  in pqisrc_init_struct_base()
377 	init_struct->err_buf_paddr_h = DMA_PHYS_HIGH(&softs->err_buf_dma_mem);  in pqisrc_init_struct_base()
378 	init_struct->err_buf_elem_len = elem_size;  in pqisrc_init_struct_base()
379 	init_struct->err_buf_num_elem = num_elem;  in pqisrc_init_struct_base()
395 	os_dma_mem_free(softs, &softs->err_buf_dma_mem);  in pqisrc_init_struct_base()
405  * - GET_ADAPTER_PROPERTIES
406  * - GET_COMM_PREFERRED_SETTINGS
407  * - GET_PQI_CAPABILITIES
408  * - INIT_STRUCT_BASE ADDR
445 	softs->pqi_reset_quiesce_allowed = false;  in pqisrc_sis_init()
447 		softs->pqi_reset_quiesce_allowed = true;  in pqisrc_sis_init()
496 	os_dma_mem_free(softs, &softs->err_buf_dma_mem);  in pqisrc_sis_uninit()
516 		db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,  in pqisrc_sis_wait_for_db_bit_to_clear()
526 			DBG_ERR("door-bell reg bit 0x%x not cleared\n", bit);  in pqisrc_sis_wait_for_db_bit_to_clear()