Lines Matching refs:SIS_CSR
229 CSR_READ_4(sc, SIS_CSR); in sis_delay()
416 csrsave = CSR_READ_4(sc, SIS_CSR); in sis_read_mac()
418 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); in sis_read_mac()
419 CSR_WRITE_4(sc, SIS_CSR, 0); in sis_read_mac()
431 CSR_WRITE_4(sc, SIS_CSR, csrsave); in sis_read_mac()
656 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); in sis_miibus_statchg()
657 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE); in sis_miibus_statchg()
842 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); in sis_reset()
845 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) in sis_reset()
1671 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); in sis_poll()
1729 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); in sis_intr()
1915 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); in sis_startl()
2061 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); in sis_initl()
2232 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); in sis_stop()
2338 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); in sis_wol()