Lines Matching +full:0 +full:x1020
30 #define ATA_DATA 0 /* (RW) data */
33 #define ATA_F_DMA 0x01 /* enable DMA */
34 #define ATA_F_OVL 0x02 /* enable overlap */
42 #define ATA_D_LBA 0x40 /* use LBA addressing */
43 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
48 #define ATA_E_ILI 0x01 /* illegal length */
49 #define ATA_E_NM 0x02 /* no media */
50 #define ATA_E_ABORT 0x04 /* command aborted */
51 #define ATA_E_MCR 0x08 /* media change request */
52 #define ATA_E_IDNF 0x10 /* ID not found */
53 #define ATA_E_MC 0x20 /* media changed */
54 #define ATA_E_UNC 0x40 /* uncorrectable data */
55 #define ATA_E_ICRC 0x80 /* UDMA crc error */
56 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
59 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
60 #define ATA_I_IN 0x02 /* read (1) | write (0) */
61 #define ATA_I_RELEASE 0x04 /* released bus (1) */
62 #define ATA_I_TAGMASK 0xf8 /* tag mask */
66 #define ATA_S_ERROR 0x01 /* error */
67 #define ATA_S_INDEX 0x02 /* index */
68 #define ATA_S_CORR 0x04 /* data corrected */
69 #define ATA_S_DRQ 0x08 /* data request */
70 #define ATA_S_DSC 0x10 /* drive seek completed */
71 #define ATA_S_SERVICE 0x10 /* drive needs service */
72 #define ATA_S_DWF 0x20 /* drive write fault */
73 #define ATA_S_DMA 0x20 /* DMA ready */
74 #define ATA_S_READY 0x40 /* drive ready */
75 #define ATA_S_BUSY 0x80 /* busy */
78 #define ATA_A_IDS 0x02 /* disable interrupts */
79 #define ATA_A_RESET 0x04 /* RESET controller */
80 #define ATA_A_4BIT 0x08 /* 4 head bits */
81 #define ATA_A_HOB 0x80 /* High Order Byte enable */
85 #define ATA_SS_DET_MASK 0x0000000f
86 #define ATA_SS_DET_NO_DEVICE 0x00000000
87 #define ATA_SS_DET_DEV_PRESENT 0x00000001
88 #define ATA_SS_DET_PHY_ONLINE 0x00000003
89 #define ATA_SS_DET_PHY_OFFLINE 0x00000004
91 #define ATA_SS_SPD_MASK 0x000000f0
92 #define ATA_SS_SPD_NO_SPEED 0x00000000
93 #define ATA_SS_SPD_GEN1 0x00000010
94 #define ATA_SS_SPD_GEN2 0x00000020
95 #define ATA_SS_SPD_GEN3 0x00000030
97 #define ATA_SS_IPM_MASK 0x00000f00
98 #define ATA_SS_IPM_NO_DEVICE 0x00000000
99 #define ATA_SS_IPM_ACTIVE 0x00000100
100 #define ATA_SS_IPM_PARTIAL 0x00000200
101 #define ATA_SS_IPM_SLUMBER 0x00000600
104 #define ATA_SE_DATA_CORRECTED 0x00000001
105 #define ATA_SE_COMM_CORRECTED 0x00000002
106 #define ATA_SE_DATA_ERR 0x00000100
107 #define ATA_SE_COMM_ERR 0x00000200
108 #define ATA_SE_PROT_ERR 0x00000400
109 #define ATA_SE_HOST_ERR 0x00000800
110 #define ATA_SE_PHY_CHANGED 0x00010000
111 #define ATA_SE_PHY_IERROR 0x00020000
112 #define ATA_SE_COMM_WAKE 0x00040000
113 #define ATA_SE_DECODE_ERR 0x00080000
114 #define ATA_SE_PARITY_ERR 0x00100000
115 #define ATA_SE_CRC_ERR 0x00200000
116 #define ATA_SE_HANDSHAKE_ERR 0x00400000
117 #define ATA_SE_LINKSEQ_ERR 0x00800000
118 #define ATA_SE_TRANSPORT_ERR 0x01000000
119 #define ATA_SE_UNKNOWN_FIS 0x02000000
122 #define ATA_SC_DET_MASK 0x0000000f
123 #define ATA_SC_DET_IDLE 0x00000000
124 #define ATA_SC_DET_RESET 0x00000001
125 #define ATA_SC_DET_DISABLE 0x00000004
127 #define ATA_SC_SPD_MASK 0x000000f0
128 #define ATA_SC_SPD_NO_SPEED 0x00000000
129 #define ATA_SC_SPD_SPEED_GEN1 0x00000010
130 #define ATA_SC_SPD_SPEED_GEN2 0x00000020
131 #define ATA_SC_SPD_SPEED_GEN3 0x00000030
133 #define ATA_SC_IPM_MASK 0x00000f00
134 #define ATA_SC_IPM_NONE 0x00000000
135 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100
136 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200
143 #define SIIS_GCTL 0x0040 /* Global Control */
144 #define SIIS_GCTL_GRESET 0x80000000 /* Global Reset */
145 #define SIIS_GCTL_MSIACK 0x40000000 /* MSI Ack */
146 #define SIIS_GCTL_I2C_IE 0x20000000 /* I2C int enable */
147 #define SIIS_GCTL_300CAP 0x01000000 /* 3Gb/s capable (R) */
149 #define SIIS_IS 0x0044 /* Interrupt Status */
150 #define SIIS_IS_I2C 0x20000000 /* I2C Int Status */
152 #define SIIS_PHYCONF 0x0048 /* PHY Configuration */
153 #define SIIS_BIST_CTL 0x0050
154 #define SIIS_BIST_PATTERN 0x0054 /* 32 bit pattern */
155 #define SIIS_BIST_STATUS 0x0058
156 #define SIIS_I2C_CTL 0x0060
157 #define SIIS_I2C_STS 0x0064
158 #define SIIS_I2C_SADDR 0x0068
159 #define SIIS_I2C_DATA 0x006C
160 #define SIIS_FLASH_ADDR 0x0070
161 #define SIIS_GPIO 0x0074
167 #define SIIS_P_LRAM 0x0000
169 #define SIIS_P_PMPSTS(i) (0x0F80 + i * 8)
170 #define SIIS_P_PMPQACT(i) (0x0F80 + i * 8 + 4)
171 #define SIIS_P_STS 0x1000
172 #define SIIS_P_CTLSET 0x1000
173 #define SIIS_P_CTLCLR 0x1004
174 #define SIIS_P_CTL_READY 0x80000000
175 #define SIIS_P_CTL_OOBB 0x02000000
176 #define SIIS_P_CTL_ACT 0x001F0000
178 #define SIIS_P_CTL_LED_ON 0x00008000
179 #define SIIS_P_CTL_AIA 0x00004000
180 #define SIIS_P_CTL_PME 0x00002000
181 #define SIIS_P_CTL_IA 0x00001000
182 #define SIIS_P_CTL_IR 0x00000800
183 #define SIIS_P_CTL_32BIT 0x00000400
184 #define SIIS_P_CTL_SCR_DIS 0x00000200
185 #define SIIS_P_CTL_CONT_DIS 0x00000100
186 #define SIIS_P_CTL_TBIST 0x00000080
187 #define SIIS_P_CTL_RESUME 0x00000040
188 #define SIIS_P_CTL_PLENGTH 0x00000020
189 #define SIIS_P_CTL_LED_DIS 0x00000010
190 #define SIIS_P_CTL_INT_NCOR 0x00000008
191 #define SIIS_P_CTL_PORT_INIT 0x00000004
192 #define SIIS_P_CTL_DEV_RESET 0x00000002
193 #define SIIS_P_CTL_PORT_RESET 0x00000001
194 #define SIIS_P_IS 0x1008
195 #define SIIS_P_IX_SDBN 0x00000800
196 #define SIIS_P_IX_HS_ET 0x00000400
197 #define SIIS_P_IX_CRC_ET 0x00000200
198 #define SIIS_P_IX_8_10_ET 0x00000100
199 #define SIIS_P_IX_DEX 0x00000080
200 #define SIIS_P_IX_UNRECFIS 0x00000040
201 #define SIIS_P_IX_COMWAKE 0x00000020
202 #define SIIS_P_IX_PHYRDYCHG 0x00000010
203 #define SIIS_P_IX_PMCHG 0x00000008
204 #define SIIS_P_IX_READY 0x00000004
205 #define SIIS_P_IX_COMMERR 0x00000002
206 #define SIIS_P_IX_COMMCOMP 0x00000001
209 #define SIIS_P_IESET 0x1010
210 #define SIIS_P_IECLR 0x1014
211 #define SIIS_P_CACTU 0x101C
212 #define SIIS_P_CMDEFIFO 0x1020
213 #define SIIS_P_CMDERR 0x1024
236 #define SIIS_P_FISCFG 0x1028
237 #define SIIS_P_PCIEFIFOTH 0x102C
238 #define SIIS_P_8_10_DEC_ERR 0x1040
239 #define SIIS_P_CRC_ERR 0x1044
240 #define SIIS_P_HS_ERR 0x1048
241 #define SIIS_P_PHYCFG 0x1050
242 #define SIIS_P_SS 0x1800
243 #define SIIS_P_SS_ATTN 0x80000000
244 #define SIIS_P_CACTL(i) (0x1C00 + i * 8)
245 #define SIIS_P_CACTH(i) (0x1C00 + i * 8 + 4)
246 #define SIIS_P_CTX 0x1E04
247 #define SIIS_P_CTX_SLOT 0x0000001F
248 #define SIIS_P_CTX_SLOT_SHIFT 0
249 #define SIIS_P_CTX_PMP 0x000001E0
252 #define SIIS_P_SCTL 0x1F00
253 #define SIIS_P_SSTS 0x1F04
254 #define SIIS_P_SERR 0x1F08
255 #define SIIS_P_SACT 0x1F0C
256 #define SIIS_P_SNTF 0x1F10
261 #define SIIS_OFFSET 0x100
262 #define SIIS_STEP 0x80
275 #define SIIS_PRD_TRM 0x80000000
276 #define SIIS_PRD_LNK 0x40000000
277 #define SIIS_PRD_DRD 0x20000000
278 #define SIIS_PRD_XCF 0x10000000
292 #define SIIS_PRB_PROTOCOL_OVERRIDE 0x0001
293 #define SIIS_PRB_RETRANSMIT 0x0002
294 #define SIIS_PRB_EXTERNAL_COMMAND 0x0004
295 #define SIIS_PRB_RECEIVE 0x0008
296 #define SIIS_PRB_PACKET_READ 0x0010
297 #define SIIS_PRB_PACKET_WRITE 0x0020
298 #define SIIS_PRB_INTERRUPT_MASK 0x0040
299 #define SIIS_PRB_SOFT_RESET 0x0080
301 #define SIIS_PRB_PROTO_PACKET 0x0001
302 #define SIIS_PRB_PROTO_TCQ 0x0002
303 #define SIIS_PRB_PROTO_NCQ 0x0004
304 #define SIIS_PRB_PROTO_READ 0x0008
305 #define SIIS_PRB_PROTO_WRITE 0x0010
306 #define SIIS_PRB_PROTO_TRANSPARENT 0x0020
316 #define ATA_IRQ_RID 0