1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
4  * Copyright (c) 2009-2016 Solarflare Communications Inc.
44 	uint32_t mask;  in siena_phy_decode_cap()  local
46 	mask = 0;  in siena_phy_decode_cap()
48 		mask |= (1 << EFX_PHY_CAP_10HDX);  in siena_phy_decode_cap()
50 		mask |= (1 << EFX_PHY_CAP_10FDX);  in siena_phy_decode_cap()
52 		mask |= (1 << EFX_PHY_CAP_100HDX);  in siena_phy_decode_cap()
54 		mask |= (1 << EFX_PHY_CAP_100FDX);  in siena_phy_decode_cap()
56 		mask |= (1 << EFX_PHY_CAP_1000HDX);  in siena_phy_decode_cap()
58 		mask |= (1 << EFX_PHY_CAP_1000FDX);  in siena_phy_decode_cap()
60 		mask |= (1 << EFX_PHY_CAP_10000FDX);  in siena_phy_decode_cap()
62 		mask |= (1 << EFX_PHY_CAP_PAUSE);  in siena_phy_decode_cap()
64 		mask |= (1 << EFX_PHY_CAP_ASYM);  in siena_phy_decode_cap()
66 		mask |= (1 << EFX_PHY_CAP_AN);  in siena_phy_decode_cap()
68 	*maskp = mask;  in siena_phy_decode_cap()
118 	efx_port_t *epp = &(enp->en_port);  in siena_phy_link_ev()
152 	 * It's safe to update ep_lp_cap_mask without the driver's port lock  in siena_phy_link_ev()
158 	 * the former, it's safe to update the value for the same reason as  in siena_phy_link_ev()
162 	epp->ep_lp_cap_mask = lp_cap_mask;  in siena_phy_link_ev()
163 	if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN))  in siena_phy_link_ev()
164 		epp->ep_fcntl = fcntl;  in siena_phy_link_ev()
183 	enp->en_reset_flags |= EFX_RESET_PHY;  in siena_phy_power()
222 			    &slsp->sls_adv_cap_mask);  in siena_phy_get_link()
224 			    &slsp->sls_lp_cap_mask);  in siena_phy_get_link()
229 			    &slsp->sls_link_mode, &slsp->sls_fcntl);  in siena_phy_get_link()
252 	slsp->sls_loopback = MCDI_OUT_DWORD(req, GET_LINK_OUT_LOOPBACK_MODE);  in siena_phy_get_link()
255 	slsp->sls_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0;  in siena_phy_get_link()
271 	efx_port_t *epp = &(enp->en_port);  in siena_phy_reconfigure()
289 	cap_mask = epp->ep_adv_cap_mask;  in siena_phy_reconfigure()
304 		    epp->ep_loopback_type);  in siena_phy_reconfigure()
305 	switch (epp->ep_loopback_link_mode) {  in siena_phy_reconfigure()
325 	MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, epp->ep_phy_flags);  in siena_phy_reconfigure()
346 	switch (epp->ep_phy_led_mode) {  in siena_phy_reconfigure()
526 			uint32_t sync;  in siena_phy_decode_stats()  local
528 			sync = EFX_DWORD_FIELD(dword, EFX_DWORD_0);  in siena_phy_decode_stats()
529 			stat[EFX_PHY_STAT_PHY_XS_SYNC_A] = (sync >> 0) & 1;  in siena_phy_decode_stats()
530 			stat[EFX_PHY_STAT_PHY_XS_SYNC_B] = (sync >> 1) & 1;  in siena_phy_decode_stats()
531 			stat[EFX_PHY_STAT_PHY_XS_SYNC_C] = (sync >> 2) & 1;  in siena_phy_decode_stats()
532 			stat[EFX_PHY_STAT_PHY_XS_SYNC_D] = (sync >> 3) & 1;  in siena_phy_decode_stats()
552 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);  in siena_phy_stats_update()
553 	uint32_t vmask = encp->enc_mcdi_phy_stat_mask;  in siena_phy_stats_update()
585 	EFSYS_ASSERT(smask == encp->enc_phy_stat_mask);  in siena_phy_stats_update()
651 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
684 	    encp->enc_phy_type == EFX_PHY_SFT9001B &&
763 		    encp->enc_phy_type == EFX_PHY_QLX111V &&