88 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);  in siena_board_cfg()  local
97 	encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;  in siena_board_cfg()
100 	encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port;  in siena_board_cfg()
107 	EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);  in siena_board_cfg()
109 	encp->enc_board_type = board_type;  in siena_board_cfg()
116 	encp->enc_hw_pf_count = 1;  in siena_board_cfg()
119 	encp->enc_clk_mult = 1;  in siena_board_cfg()
125 			encp->enc_clk_mult = 2;  in siena_board_cfg()
129 	encp->enc_evq_timer_quantum_ns =  in siena_board_cfg()
130 		EFX_EVQ_SIENA_TIMER_QUANTUM_NS / encp->enc_clk_mult;  in siena_board_cfg()
131 	encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<  in siena_board_cfg()
135 	encp->enc_rx_prefix_size = 16;  in siena_board_cfg()
138 	encp->enc_rx_buf_align_start = 1;  in siena_board_cfg()
139 	encp->enc_rx_buf_align_end = 1;  in siena_board_cfg()
142 	encp->enc_rx_push_align = 1;  in siena_board_cfg()
146 	encp->enc_rx_scale_max_exclusive_contexts = 1;  in siena_board_cfg()
148 	encp->enc_rx_scale_hash_alg_mask |= (1U << EFX_RX_HASHALG_LFSR);  in siena_board_cfg()
149 	encp->enc_rx_scale_hash_alg_mask |= (1U << EFX_RX_HASHALG_TOEPLITZ);  in siena_board_cfg()
155 	encp->enc_rx_scale_l4_hash_supported = B_TRUE;  in siena_board_cfg()
158 	encp->enc_rx_scale_additional_modes_supported = B_FALSE;  in siena_board_cfg()
161 	encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);  in siena_board_cfg()
163 	encp->enc_tx_dma_desc_boundary = 4096;  in siena_board_cfg()
175 	encp->enc_evq_limit = nevq;  in siena_board_cfg()
176 	encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);  in siena_board_cfg()
177 	encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);  in siena_board_cfg()
179 	encp->enc_txq_max_ndescs = 4096;  in siena_board_cfg()
181 	encp->enc_buftbl_limit = SIENA_SRAM_ROWS -  in siena_board_cfg()
182 	    (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -  in siena_board_cfg()
183 	    (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));  in siena_board_cfg()
185 	encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;  in siena_board_cfg()
186 	encp->enc_fw_assisted_tso_enabled = B_FALSE;  in siena_board_cfg()
187 	encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;  in siena_board_cfg()
188 	encp->enc_fw_assisted_tso_v2_n_contexts = 0;  in siena_board_cfg()
189 	encp->enc_allow_set_mac_with_installed_filters = B_TRUE;  in siena_board_cfg()
190 	encp->enc_rx_packed_stream_supported = B_FALSE;  in siena_board_cfg()
191 	encp->enc_rx_var_packed_stream_supported = B_FALSE;  in siena_board_cfg()
192 	encp->enc_rx_es_super_buffer_supported = B_FALSE;  in siena_board_cfg()
193 	encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;  in siena_board_cfg()
196 	encp->enc_required_pcie_bandwidth_mbps = 2 * 10000;  in siena_board_cfg()
197 	encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN2;  in siena_board_cfg()
199 	encp->enc_nvram_update_verify_result_supported = B_FALSE;  in siena_board_cfg()
201 	encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;  in siena_board_cfg()
203 	encp->enc_filter_action_flag_supported = B_FALSE;  in siena_board_cfg()
204 	encp->enc_filter_action_mark_supported = B_FALSE;  in siena_board_cfg()
205 	encp->enc_filter_action_mark_max = 0;  in siena_board_cfg()
222 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);  in siena_phy_cfg()  local
232 	siena_phy_decode_stats(enp, encp->enc_mcdi_phy_stat_mask,  in siena_phy_cfg()
233 			    NULL, &encp->enc_phy_stat_mask, NULL);  in siena_phy_cfg()
320 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);  in siena_nic_probe()  local
388 	encp->enc_features = enp->en_features;  in siena_nic_probe()