Lines Matching +full:0 +full:x00018000
49 * SPI/VPD configuration register 0
51 #define FR_AB_EE_VPD_CFG0_REG_SF_OFST 0x00000300
55 * SPI/VPD configuration register 0
57 #define FR_AB_EE_VPD_CFG0_REG_OFST 0x00000140
90 #define FRF_AB_EE_VPD_EN_LBN 0
95 * PCIE SerDes control register 0 to 3
97 #define FR_AB_PCIE_SD_CTL0123_REG_SF_OFST 0x00000320
101 * PCIE SerDes control register 0 to 3
103 #define FR_AB_PCIE_SD_CTL0123_REG_OFST 0x00000320
139 #define FFE_AB_PCIE_RXTERMADJ_NOMNL 0
147 #define FFE_AB_PCIE_TXTERMADJ_NOMNL 0
155 #define FFE_AB_PCIE_RXEQCTL_MAX 0
158 #define FRF_AB_PCIE_LODRV_LBN 0
165 #define FR_AB_PCIE_SD_CTL45_REG_SF_OFST 0x00000330
171 #define FR_AB_PCIE_SD_CTL45_REG_OFST 0x00000330
204 #define FRF_AB_PCIE_DEQ0_LBN 0
211 #define FR_AB_PCIE_PCS_CTL_STAT_REG_SF_OFST 0x00000340
217 #define FR_AB_PCIE_PCS_CTL_STAT_REG_OFST 0x00000340
244 #define FRF_AB_PCIE_PRBSSEL_LBN 0
251 #define FR_AB_HW_INIT_REG_SF_OFST 0x00000350
257 #define FR_AZ_HW_INIT_REG_OFST 0x000000c0
298 #define FRF_AZ_TLP_TD_LBN 0
305 #define FR_AB_NIC_STAT_REG_SF_OFST 0x00000360
311 #define FR_AB_NIC_STAT_REG_OFST 0x00000200
330 #define FRF_AB_STRAP_PINS_LBN 0
337 #define FR_AB_GLB_CTL_REG_SF_OFST 0x00000370
343 #define FR_AB_GLB_CTL_REG_OFST 0x00000220
427 #define FFE_AB_EXT_PHY_RST_DUR_80US 0
428 #define FRF_AB_SWRST_LBN 0
435 #define FR_AZ_IOM_IND_ADR_REG_OFST 0x00000000
440 #define FRF_AZ_IOM_IND_ADR_LBN 0
447 #define FR_AZ_IOM_IND_DAT_REG_OFST 0x00000004
450 #define FRF_AZ_IOM_IND_DAT_LBN 0
457 #define FR_AZ_ADR_REGION_REG_OFST 0x00000000
466 #define FRF_AZ_ADR_REGION0_LBN 0
473 #define FR_AZ_INT_EN_REG_KER_OFST 0x00000010
482 #define FRF_AZ_DRV_INT_EN_KER_LBN 0
489 #define FR_AZ_INT_EN_REG_CHAR_OFST 0x00000020
498 #define FRF_AZ_DRV_INT_EN_CHAR_LBN 0
505 #define FR_AZ_INT_ADR_REG_KER_OFST 0x00000030
510 #define FRF_AZ_INT_ADR_KER_LBN 0
512 #define FRF_AZ_INT_ADR_KER_DW0_LBN 0
521 #define FR_AZ_INT_ADR_REG_CHAR_OFST 0x00000040
526 #define FRF_AZ_INT_ADR_CHAR_LBN 0
528 #define FRF_AZ_INT_ADR_CHAR_DW0_LBN 0
537 #define FR_AA_INT_ACK_KER_OFST 0x00000050
540 #define FRF_AA_INT_ACK_KER_FIELD_LBN 0
545 * Function 0 Interrupt Acknowlege Status register
547 #define FR_BZ_INT_ISR0_REG_OFST 0x00000090
550 #define FRF_BZ_INT_ISR_REG_LBN 0
552 #define FRF_BZ_INT_ISR_REG_DW0_LBN 0
561 #define FR_AB_EE_SPI_HCMD_REG_OFST 0x00000100
578 #define FRF_AB_EE_SPI_HCMD_ENC_LBN 0
585 #define FR_CZ_USR_EV_CFG_OFST 0x00000100
590 #define FRF_CZ_DFLT_EVQ_LBN 0
597 #define FR_AB_EE_SPI_HADR_REG_OFST 0x00000110
602 #define FRF_AB_EE_SPI_HADR_ADR_LBN 0
609 #define FR_AB_EE_SPI_HDATA_REG_OFST 0x00000120
618 #define FRF_AB_EE_SPI_HDATA0_LBN 0
625 #define FR_AB_EE_BASE_PAGE_REG_OFST 0x00000130
630 #define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0
637 #define FR_AB_EE_VPD_SW_CNTL_REG_OFST 0x00000150
644 #define FRF_AB_EE_VPD_CYC_ADR_LBN 0
651 #define FR_AB_EE_VPD_SW_DATA_REG_OFST 0x00000160
654 #define FRF_AB_EE_VPD_CYC_DAT_LBN 0
661 #define FR_BB_PCIE_CORE_INDIRECT_REG_OFST 0x000001f0
668 #define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0
675 #define FR_AB_GPIO_CTL_REG_OFST 0x00000210
792 #define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0
799 #define FR_AZ_FATAL_INTR_REG_KER_OFST 0x00000230
856 #define FRF_AZ_SRM_PERR_INT_KER_LBN 0
863 #define FR_AZ_FATAL_INTR_REG_CHAR_OFST 0x00000240
920 #define FRF_AZ_SRM_PERR_INT_CHAR_LBN 0
927 #define FR_AZ_DP_CTRL_REG_OFST 0x00000250
930 #define FRF_AZ_FLS_EVQ_ID_LBN 0
937 #define FR_AZ_MEM_STAT_REG_OFST 0x00000260
948 #define FRF_AB_MBIST_ERR_LBN 0
950 #define FRF_AB_MBIST_ERR_DW0_LBN 0
954 #define FRF_CZ_MEM_PERR_VEC_LBN 0
956 #define FRF_CZ_MEM_PERR_VEC_DW0_LBN 0
966 #define FR_AZ_CS_DEBUG_REG_OFST 0x00000270
1003 #define FRF_AZ_CS_DEBUG_EN_LBN 0
1008 * Driver scratch register [0-7]
1010 #define FR_AZ_DRIVER_REG_OFST 0x00000280
1015 #define FRF_AZ_DRIVER_DW0_LBN 0
1022 #define FR_AZ_ALTERA_BUILD_REG_OFST 0x00000300
1025 #define FRF_AZ_ALTERA_BUILD_VER_LBN 0
1032 #define FR_AZ_CSR_SPARE_REG_OFST 0x00000310
1043 #define FRF_AZ_CSR_SPARE_BITS_LBN 0
1050 #define FR_BZ_DEBUG_DATA_OUT_REG_OFST 0x00000350
1055 #define FRF_BZ_DEBUG1_PORT_LBN 0
1062 #define FR_BZ_EVQ_RPTR_REGP0_OFST 0x00000400
1070 #define FR_AA_EVQ_RPTR_REG_KER_OFST 0x00011b00
1078 #define FR_AZ_EVQ_RPTR_REG_OFST 0x00fa0000
1087 #define FR_BB_EVQ_RPTR_REGP123_OFST 0x01000400
1094 #define FRF_AZ_EVQ_RPTR_LBN 0
1101 #define FR_BZ_TIMER_COMMAND_REGP0_OFST 0x00000420
1109 #define FR_AA_TIMER_COMMAND_REG_KER_OFST 0x00000420
1117 #define FR_AB_TIMER_COMMAND_REGP123_OFST 0x01000420
1125 #define FR_AA_TIMER_COMMAND_REGP0_OFST 0x00008420
1134 #define FRF_CZ_TC_TIMER_VAL_LBN 0
1136 #define FRF_AB_TC_TIMER_VAL_LBN 0
1143 #define FR_AZ_DRV_EV_REG_OFST 0x00000440
1148 #define FRF_AZ_DRV_EV_DATA_LBN 0
1150 #define FRF_AZ_DRV_EV_DATA_DW0_LBN 0
1159 #define FR_AZ_EVQ_CTL_REG_OFST 0x00000450
1170 #define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0
1177 #define FR_AZ_EVQ_CNT1_REG_OFST 0x00000460
1192 #define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0
1199 #define FR_AZ_EVQ_CNT2_REG_OFST 0x00000470
1214 #define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0
1221 #define FR_CZ_USR_EV_REG_OFST 0x00000540
1226 #define FRF_CZ_USR_EV_DATA_LBN 0
1233 #define FR_AZ_BUF_TBL_CFG_REG_OFST 0x00000600
1243 #define FR_AZ_SRM_RX_DC_CFG_REG_OFST 0x00000610
1248 #define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0
1255 #define FR_AZ_SRM_TX_DC_CFG_REG_OFST 0x00000620
1258 #define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0
1265 #define FR_AZ_SRM_CFG_REG_SF_OFST 0x00000380
1271 #define FR_AZ_SRM_CFG_REG_OFST 0x00000630
1282 #define FRF_AZ_SRM_BANK_SIZE_LBN 0
1289 #define FR_AZ_BUF_TBL_UPD_REG_OFST 0x00000650
1298 #define FRF_AZ_BUF_CLR_START_ID_LBN 0
1305 #define FR_AZ_SRM_UPD_EVQ_REG_OFST 0x00000660
1308 #define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0
1315 #define FR_AZ_SRAM_PARITY_REG_OFST 0x00000670
1324 #define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0
1326 #define FRF_AB_FORCE_SRAM_PERR_LBN 0
1333 #define FR_AZ_RX_CFG_REG_OFST 0x00000800
1390 #define FRF_AZ_RX_XOFF_MAC_EN_LBN 0
1397 #define FR_AZ_RX_FILTER_CTL_REG_OFST 0x00000810
1430 #define FRF_AZ_TCP_FULL_SRCH_LIMIT_LBN 0
1437 #define FR_AZ_RX_FLUSH_DESCQ_REG_OFST 0x00000820
1442 #define FRF_AZ_RX_FLUSH_DESCQ_LBN 0
1449 #define FR_BZ_RX_DESC_UPD_REGP0_OFST 0x00000830
1457 #define FR_AA_RX_DESC_UPD_REG_KER_OFST 0x00000830
1465 #define FR_AB_RX_DESC_UPD_REGP123_OFST 0x01000830
1473 #define FR_AA_RX_DESC_UPD_REGP0_OFST 0x00008830
1482 #define FRF_AZ_RX_DESC_LBN 0
1484 #define FRF_AZ_RX_DESC_DW0_LBN 0
1493 #define FR_AZ_RX_DC_CFG_REG_OFST 0x00000840
1498 #define FRF_AZ_RX_DC_SIZE_LBN 0
1503 #define FFE_AZ_RX_DC_SIZE_8 0
1509 #define FR_AZ_RX_DC_PF_WM_REG_OFST 0x00000850
1514 #define FRF_AZ_RX_DC_PF_LWM_LBN 0
1521 #define FR_BZ_RX_RSS_TKEY_REG_OFST 0x00000860
1532 #define FRF_BZ_RX_RSS_TKEY_DW0_LBN 0
1539 #define FR_AZ_RX_NODESC_DROP_REG_OFST 0x00000880
1542 #define FRF_AZ_RX_NODESC_DROP_CNT_LBN 0
1549 #define FR_AZ_RX_SELF_RST_REG_OFST 0x00000890
1560 #define FRF_AZ_RX_MAX_LU_LAT_LBN 0
1567 #define FR_AZ_RX_DEBUG_REG_OFST 0x000008a0
1570 #define FRF_AZ_RX_DEBUG_LBN 0
1572 #define FRF_AZ_RX_DEBUG_DW0_LBN 0
1581 #define FR_AZ_RX_PUSH_DROP_REG_OFST 0x000008b0
1584 #define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0
1591 #define FR_CZ_RX_RSS_IPV6_REG1_OFST 0x000008d0
1594 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0
1596 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_LBN 0
1609 #define FR_CZ_RX_RSS_IPV6_REG2_OFST 0x000008e0
1612 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0
1614 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_LBN 0
1627 #define FR_CZ_RX_RSS_IPV6_REG3_OFST 0x000008f0
1636 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0
1638 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_LBN 0
1647 #define FR_AZ_TX_FLUSH_DESCQ_REG_OFST 0x00000a00
1652 #define FRF_AZ_TX_FLUSH_DESCQ_LBN 0
1659 #define FR_BZ_TX_DESC_UPD_REGP0_OFST 0x00000a10
1667 #define FR_AA_TX_DESC_UPD_REG_KER_OFST 0x00000a10
1675 #define FR_AB_TX_DESC_UPD_REGP123_OFST 0x01000a10
1683 #define FR_AA_TX_DESC_UPD_REGP0_OFST 0x00008a10
1692 #define FRF_AZ_TX_DESC_LBN 0
1694 #define FRF_AZ_TX_DESC_DW0_LBN 0
1705 #define FR_AZ_TX_DC_CFG_REG_OFST 0x00000a20
1708 #define FRF_AZ_TX_DC_SIZE_LBN 0
1712 #define FFE_AZ_TX_DC_SIZE_8 0
1718 #define FR_AA_TX_CHKSM_CFG_REG_OFST 0x00000a30
1727 #define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0
1734 #define FR_AZ_TX_CFG_REG_OFST 0x00000a50
1769 #define FRF_AZ_TX_IP_ID_REP_EN_LBN 0
1776 #define FR_AZ_TX_PUSH_DROP_REG_OFST 0x00000a60
1779 #define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0
1786 #define FR_AZ_TX_RESERVED_REG_OFST 0x00000a80
1844 #define FFE_AZ_TX_MAX_CPL_NOLIMIT 0
1845 #define FRF_AZ_TX_MAX_PREF_LBN 0
1850 #define FFE_AZ_TX_MAX_PREF_OFF 0
1856 #define FR_BZ_TX_PACE_REG_OFST 0x00000a90
1862 #define FR_AA_TX_PACE_REG_OFST 0x00f80000
1871 #define FRF_AZ_TX_PACE_BIN_TH_LBN 0
1878 #define FR_AZ_TX_PACE_DROP_QID_REG_OFST 0x00000aa0
1881 #define FRF_AZ_TX_PACE_QID_DRP_CNT_LBN 0
1888 #define FR_AB_TX_VLAN_REG_OFST 0x00000ae0
1939 #define FRF_AB_TX_VLAN0_LBN 0
1946 #define FR_AZ_TX_IPFIL_PORTEN_REG_OFST 0x00000af0
2013 #define FRF_AB_TX_IPFIL0_PORT_EN_LBN 0
2020 #define FR_AB_TX_IPFIL_TBL_OFST 0x00000b00
2031 #define FRF_AB_TX_IP_SRC_ADR_0_LBN 0
2038 #define FR_AB_MD_TXD_REG_OFST 0x00000c00
2041 #define FRF_AB_MD_TXD_LBN 0
2048 #define FR_AB_MD_RXD_REG_OFST 0x00000c10
2051 #define FRF_AB_MD_RXD_LBN 0
2058 #define FR_AB_MD_CS_REG_OFST 0x00000c20
2081 #define FRF_AB_MD_WRC_LBN 0
2088 #define FR_AB_MD_PHY_ADR_REG_OFST 0x00000c30
2091 #define FRF_AB_MD_PHY_ADR_LBN 0
2098 #define FR_AB_MD_ID_REG_OFST 0x00000c40
2110 #define FR_AB_MD_STAT_REG_OFST 0x00000c50
2121 #define FRF_AB_MD_BSY_LBN 0
2128 #define FR_AB_MAC_STAT_DMA_REG_OFST 0x00000c60
2133 #define FRF_AB_MAC_STAT_DMA_ADR_LBN 0
2135 #define FRF_AB_MAC_STAT_DMA_ADR_DW0_LBN 0
2144 #define FR_AB_MAC_CTRL_REG_OFST 0x00000c80
2159 #define FRF_AB_MAC_SPEED_LBN 0
2161 #define FRF_AB_MAC_SPEED_10M 0
2170 #define FR_BB_GEN_MODE_REG_OFST 0x00000c90
2179 #define FRF_BB_XG_PHY_INT_MASK_LBN 0
2186 #define FR_AB_MAC_MC_HASH0_REG_OFST 0x00000ca0
2189 #define FRF_AB_MAC_MCAST_HASH0_LBN 0
2191 #define FRF_AB_MAC_MCAST_HASH0_DW0_LBN 0
2204 #define FR_AB_MAC_MC_HASH1_REG_OFST 0x00000cb0
2207 #define FRF_AB_MAC_MCAST_HASH1_LBN 0
2209 #define FRF_AB_MAC_MCAST_HASH1_DW0_LBN 0
2222 #define FR_AB_GM_CFG1_REG_OFST 0x00000e00
2249 #define FRF_AB_GM_TX_EN_LBN 0
2256 #define FR_AB_GM_CFG2_REG_OFST 0x00000e10
2273 #define FRF_AB_GM_FD_LBN 0
2280 #define FR_AB_GM_IPG_REG_OFST 0x00000e20
2289 #define FRF_AB_GM_B2B_IPG_LBN 0
2296 #define FR_AB_GM_HD_REG_OFST 0x00000e30
2311 #define FRF_AB_GM_COL_WIN_LBN 0
2318 #define FR_AB_GM_MAX_FLEN_REG_OFST 0x00000e40
2321 #define FRF_AB_GM_MAX_FLEN_LBN 0
2328 #define FR_AB_GM_TEST_REG_OFST 0x00000e70
2337 #define FRF_AB_GM_SHORT_SLOT_LBN 0
2344 #define FR_AB_GM_ADR1_REG_OFST 0x00000f00
2353 #define FRF_AB_GM_ADR_B3_LBN 0
2360 #define FR_AB_GM_ADR2_REG_OFST 0x00000f10
2370 * GMAC FIFO configuration register 0
2372 #define FR_AB_GMF_CFG0_REG_OFST 0x00000f20
2403 #define FRF_AB_GMF_HSTRSTWT_LBN 0
2410 #define FR_AB_GMF_CFG1_REG_OFST 0x00000f30
2415 #define FRF_AB_GMF_CFGXOFFRTX_LBN 0
2422 #define FR_AB_GMF_CFG2_REG_OFST 0x00000f40
2427 #define FRF_AB_GMF_CFGLWM_LBN 0
2434 #define FR_AB_GMF_CFG3_REG_OFST 0x00000f50
2439 #define FRF_AB_GMF_CFGFTTH_LBN 0
2446 #define FR_AB_GMF_CFG4_REG_OFST 0x00000f60
2449 #define FRF_AB_GMF_HSTFLTRFRM_LBN 0
2456 #define FR_AB_GMF_CFG5_REG_OFST 0x00000f70
2469 #define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0
2476 #define FR_BB_TX_SRC_MAC_TBL_OFST 0x00001000
2487 #define FRF_BB_TX_SRC_MAC_ADR_0_LBN 0
2489 #define FRF_BB_TX_SRC_MAC_ADR_0_DW0_LBN 0
2498 #define FR_BB_TX_SRC_MAC_CTL_REG_OFST 0x00001100
2507 #define FRF_BB_TX_MAC_QID_SEL_LBN 0
2514 #define FR_AB_XM_ADR_LO_REG_OFST 0x00001200
2517 #define FRF_AB_XM_ADR_LO_LBN 0
2524 #define FR_AB_XM_ADR_HI_REG_OFST 0x00001210
2527 #define FRF_AB_XM_ADR_HI_LBN 0
2534 #define FR_AB_XM_GLB_CFG_REG_OFST 0x00001220
2551 #define FRF_AB_XM_CORE_RST_LBN 0
2558 #define FR_AB_XM_TX_CFG_REG_OFST 0x00001230
2577 #define FRF_AB_XM_TX_RST_LBN 0
2584 #define FR_AB_XM_RX_CFG_REG_OFST 0x00001240
2607 #define FRF_AB_XM_RX_RST_LBN 0
2614 #define FR_AB_XM_MGT_INT_MASK_OFST 0x00001250
2627 #define FRF_AB_XM_MSK_LCLFLT_LBN 0
2634 #define FR_AB_XM_FC_REG_OFST 0x00001270
2653 #define FRF_AB_XM_DIS_FCNTL_LBN 0
2660 #define FR_AB_XM_PAUSE_TIME_REG_OFST 0x00001290
2665 #define FRF_AB_XM_RX_PAUSE_CNT_LBN 0
2672 #define FR_AB_XM_TX_PARAM_REG_OFST 0x000012d0
2681 #define FRF_AB_XM_PAD_CHAR_LBN 0
2688 #define FR_AB_XM_RX_PARAM_REG_OFST 0x000012e0
2693 #define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0
2700 #define FR_AB_XM_MGT_INT_REG_OFST 0x000012f0
2711 #define FRF_AB_XM_LCLFLT_LBN 0
2718 #define FR_AB_XX_PWR_RST_REG_OFST 0x00001300
2773 #define FRF_AB_XX_RST_XX_EN_LBN 0
2780 #define FR_AB_XX_SD_CTL_REG_OFST 0x00001310
2809 #define FRF_AB_XX_LPBKA_LBN 0
2816 #define FR_AB_XX_TXDRV_CTL_REG_OFST 0x00001320
2833 #define FRF_AB_XX_DTXA_LBN 0
2840 #define FR_AB_XX_PRBS_CTL_REG_OFST 0x00001330
2889 #define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0
2896 #define FR_AB_XX_PRBS_CHK_REG_OFST 0x00001340
2931 #define FRF_AB_XX_CH0_ERR_CHK_LBN 0
2938 #define FR_AB_XX_PRBS_ERR_REG_OFST 0x00001350
2947 #define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0
2954 #define FR_AB_XX_CORE_STAT_REG_OFST 0x00001360
3019 #define FRF_AB_XX_DISPERR_CH0_LBN 0
3026 #define FR_AA_RX_DESC_PTR_TBL_KER_OFST 0x00011800
3034 #define FR_AZ_RX_DESC_PTR_TBL_OFST 0x00f40000
3069 #define FFE_AZ_RX_DESCQ_SIZE_512 0
3074 #define FRF_AZ_RX_DESCQ_EN_LBN 0
3081 #define FR_AA_TX_DESC_PTR_TBL_KER_OFST 0x00011900
3089 #define FR_AZ_TX_DESC_PTR_TBL_OFST 0x00f50000
3132 #define FFE_AZ_TX_DESCQ_SIZE_512 0
3135 #define FRF_AZ_TX_DESCQ_FLUSH_LBN 0
3142 #define FR_AA_EVQ_PTR_TBL_KER_OFST 0x00011a00
3150 #define FR_AZ_EVQ_PTR_TBL_OFST 0x00f60000
3172 #define FFE_AZ_EVQ_SIZE_512 0
3173 #define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0
3180 #define FR_AA_BUF_HALF_TBL_KER_OFST 0x00018000
3188 #define FR_AZ_BUF_HALF_TBL_OFST 0x00800000
3200 #define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0
3207 #define FR_AA_BUF_FULL_TBL_KER_OFST 0x00018000
3215 #define FR_AZ_BUF_FULL_TBL_OFST 0x00800000
3231 #define FFE_AZ_BUF_ADR_REGN0 0
3238 #define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0
3245 #define FR_AZ_RX_FILTER_TBL0_OFST 0x00f00000
3253 #define FR_AB_RX_FILTER_TBL1_OFST 0x00f00010
3272 #define FRF_AZ_SRC_TCP_DEST_UDP_LBN 0
3279 #define FR_CZ_RX_MAC_FILTER_TBL0_OFST 0x00f00010
3300 #define FRF_CZ_RMFT_VLAN_ID_LBN 0
3307 #define FR_AZ_TIMER_TBL_OFST 0x00f70000
3328 #define FFE_CZ_TIMER_MODE_DIS 0
3334 #define FFE_AB_TIMER_MODE_DIS 0
3335 #define FRF_CZ_TIMER_VAL_LBN 0
3337 #define FRF_AB_TIMER_VAL_LBN 0
3344 #define FR_BZ_TX_PACE_TBL_OFST 0x00f80000
3353 #define FR_AA_TX_PACE_TBL_OFST 0x00f80040
3358 #define FRF_AZ_TX_PACE_LBN 0
3365 #define FR_BZ_RX_INDIRECTION_TBL_OFST 0x00fb0000
3370 #define FRF_BZ_IT_QUEUE_LBN 0
3377 #define FR_CZ_TX_FILTER_TBL0_OFST 0x00fc0000
3392 #define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0
3399 #define FR_CZ_TX_MAC_FILTER_TBL0_OFST 0x00fe0000
3414 #define FRF_CZ_TMFT_VLAN_ID_LBN 0
3421 #define FR_CZ_MC_TREG_SMEM_OFST 0x00ff0000
3426 #define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0
3433 #define FR_BB_MSIX_VECTOR_TABLE_OFST 0x00ff0000
3441 #define FR_CZ_MSIX_VECTOR_TABLE_OFST 0x00000000
3454 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0
3461 #define FR_BB_MSIX_PBA_TABLE_OFST 0x00ff2000
3469 #define FR_CZ_MSIX_PBA_TABLE_OFST 0x00008000
3474 #define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0
3481 #define FR_AZ_SRM_DBG_REG_OFST 0x03000000
3488 #define FRF_AZ_SRM_DBG_LBN 0
3490 #define FRF_AZ_SRM_DBG_DW0_LBN 0
3499 #define FR_AA_INT_ACK_CHAR_OFST 0x00000060
3502 #define FRF_AA_INT_ACK_CHAR_FIELD_LBN 0
3518 #define FSE_AZ_TX_DESCQ_FLS_DONE_EV 0
3519 #define FSF_AZ_DRIVER_EV_SUBDATA_LBN 0
3530 #define FSE_AZ_EV_CODE_RX_EV 0
3531 #define FSF_AZ_EV_DATA_LBN 0
3533 #define FSF_AZ_EV_DATA_DW0_LBN 0
3580 #define FSE_AZ_RX_EV_PKT_TYPE_ETH 0
3588 #define FSE_AZ_RX_EV_HDR_TYPE_IPV4_TCP 0
3589 #define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0
3614 #define FSF_AZ_RX_EV_DESC_PTR_LBN 0
3622 #define FSF_AZ_RX_KER_BUF_ADDR_LBN 0
3624 #define FSF_AZ_RX_KER_BUF_ADDR_DW0_LBN 0
3632 #define FSF_AZ_RX_USER_BUF_ID_LBN 0
3650 #define FSF_AZ_TX_EV_DESC_PTR_LBN 0
3660 #define FSF_AZ_TX_KER_BUF_ADDR_LBN 0
3662 #define FSF_AZ_TX_KER_BUF_ADDR_DW0_LBN 0
3676 #define FSF_AZ_TX_USER_BYTE_OFS_LBN 0
3682 #define FSF_CZ_USER_EV_REG_VALUE_LBN 0
3694 #define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0
3701 #define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0