Lines Matching defs:efx_nic_cfg_s
1282 typedef struct efx_nic_cfg_s { struct
1283 uint32_t enc_board_type;
1284 uint32_t enc_phy_type;
1286 char enc_phy_name[21];
1288 char enc_phy_revision[21];
1289 efx_mon_type_t enc_mon_type;
1291 uint32_t enc_mon_stat_dma_buf_size;
1292 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1294 unsigned int enc_features;
1295 efx_vi_window_shift_t enc_vi_window_shift;
1296 uint8_t enc_mac_addr[6];
1297 uint8_t enc_port; /* PHY port number */
1298 uint32_t enc_intr_vec_base;
1299 uint32_t enc_intr_limit;
1300 uint32_t enc_evq_limit;
1301 uint32_t enc_txq_limit;
1302 uint32_t enc_rxq_limit;
1303 uint32_t enc_txq_max_ndescs;
1304 uint32_t enc_buftbl_limit;
1305 uint32_t enc_piobuf_limit;
1306 uint32_t enc_piobuf_size;
1307 uint32_t enc_piobuf_min_alloc_size;
1308 uint32_t enc_evq_timer_quantum_ns;
1309 uint32_t enc_evq_timer_max_us;
1310 uint32_t enc_clk_mult;
1311 uint32_t enc_rx_prefix_size;
1312 uint32_t enc_rx_buf_align_start;
1313 uint32_t enc_rx_buf_align_end;
1315 uint32_t enc_rx_scale_max_exclusive_contexts;
1320 uint32_t enc_rx_scale_hash_alg_mask;
1325 boolean_t enc_rx_scale_l4_hash_supported;
1326 boolean_t enc_rx_scale_additional_modes_supported;
1329 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1332 uint32_t enc_phy_flags_mask;
1335 uint32_t enc_led_mask;
1338 uint64_t enc_phy_stat_mask;
1341 uint8_t enc_mcdi_mdio_channel;
1343 uint32_t enc_mcdi_phy_stat_mask;
1346 uint32_t *enc_mcdi_sensor_maskp;
1347 uint32_t enc_mcdi_sensor_mask_size;
1351 uint32_t enc_bist_mask;
1354 uint32_t enc_pf;
1355 uint32_t enc_vf;
1356 uint32_t enc_privilege_mask;
1358 boolean_t enc_bug26807_workaround;
1359 boolean_t enc_bug35388_workaround;
1360 boolean_t enc_bug41750_workaround;
1361 boolean_t enc_bug61265_workaround;
1362 boolean_t enc_bug61297_workaround;
1363 boolean_t enc_rx_batching_enabled;
1365 uint32_t enc_rx_batch_max;
1367 uint32_t enc_rx_push_align;
1369 uint32_t enc_tx_dma_desc_size_max;
1374 uint32_t enc_tx_dma_desc_boundary;
1379 uint32_t enc_tx_tso_tcp_header_offset_limit;
1380 boolean_t enc_fw_assisted_tso_enabled;
1381 boolean_t enc_fw_assisted_tso_v2_enabled;
1382 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1384 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1385 boolean_t enc_hw_tx_insert_vlan_enabled;
1387 uint32_t enc_hw_pf_count;
1389 boolean_t enc_datapath_cap_evb;
1390 boolean_t enc_rx_disable_scatter_supported;
1391 boolean_t enc_allow_set_mac_with_installed_filters;
1392 boolean_t enc_enhanced_set_mac_supported;
1393 boolean_t enc_init_evq_v2_supported;
1394 boolean_t enc_rx_packed_stream_supported;
1395 boolean_t enc_rx_var_packed_stream_supported;
1396 boolean_t enc_rx_es_super_buffer_supported;
1397 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1398 boolean_t enc_pm_and_rxdp_counters;
1399 boolean_t enc_mac_stats_40g_tx_size_bins;
1400 uint32_t enc_tunnel_encapsulations_supported;
1405 uint32_t enc_tunnel_config_udp_entries_max;
1407 uint8_t enc_external_port;
1408 uint32_t enc_mcdi_max_payload_length;
1410 boolean_t enc_vpd_is_global;
1412 uint32_t enc_required_pcie_bandwidth_mbps;
1413 uint32_t enc_max_pcie_link_gen;
1415 uint32_t enc_nvram_update_verify_result_supported;
1417 uint32_t enc_mac_stats_nstats;
1418 boolean_t enc_fec_counters;
1419 boolean_t enc_hlb_counters;
1421 boolean_t enc_filter_action_flag_supported;
1422 boolean_t enc_filter_action_mark_supported;
1423 uint32_t enc_filter_action_mark_max;