Lines Matching refs:uint16_t

119   uint16_t type_id;
124   uint16_t preset;
156   uint16_t type_id;
157   uint16_t reserved;
191   uint16_t reserved;
192   uint16_t count;
193   uint16_t stride;
258     uint16_t addr;
259     uint16_t byte_enables;
270     uint16_t addr;
271     uint16_t byte_enables;
308   uint16_t version_w;
309   uint16_t version_x;
310   uint16_t version_y;
311   uint16_t version_z;
322   uint16_t pf_aper;                             /**< BIU aperture for PF BAR2 */
323   uint16_t vf_aper;                             /**< BIU aperture for VF BAR0 */
324   uint16_t int_aper;                            /**< BIU aperture for PF BAR4 and VF BAR2 */
341   uint16_t vectors_per_pf;
342   uint16_t vectors_per_vf;
347   uint16_t supp_pagesz;
348   uint16_t msix_vec_base;
440   uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
442   uint16_t target_voltage; /* In millivolts */
445   uint16_t warn_low;       /* In millivolts */
446   uint16_t warn_high;      /* In millivolts */
447   uint16_t panic_low;      /* In millivolts */
448   uint16_t panic_high;     /* In millivolts */
459   uint16_t clk_sys;        /* MHz */
460   uint16_t clk_dpcpu;      /* MHz */
461   uint16_t clk_icore;      /* MHz */
462   uint16_t clk_pcs;        /* MHz */
470   uint16_t clk_sys;        /* MHz */
471   uint16_t clk_mc;         /* MHz */
472   uint16_t clk_rmon;       /* MHz */
473   uint16_t clk_vswitch;    /* MHz */
474   uint16_t clk_dpcpu;      /* MHz */
475   uint16_t clk_pcs;        /* MHz */
491   uint16_t reserved1;
492   uint16_t count;
493   uint16_t reserved2;
504   uint16_t millivolts;
505   uint16_t reserved;
529   uint16_t visible_pfs;                         /**< Bitmap of visible PFs */
530   uint16_t pf_aper;                             /**< BIU aperture for PF BAR2 */
531   uint16_t vf_aper;                             /**< BIU aperture for VF BAR0 */
532   uint16_t int_aper;                            /**< BIU aperture for PF BAR4 and VF BAR2 */
653   uint16_t reserved;
801   uint16_t vi_count;
828   uint16_t gen;   /* Target PCIe generation: 1, 2, 3 */
829   uint16_t width; /* Number of lanes */
1010   uint16_t ports[];