1 /*-
2  * Copyright (c) 2012-2016 Solarflare Communications Inc.
48  * systems which are little-endian and do not do strange things with structure
49  * padding.  (Big-endian host systems will require some byte-swapping.)
51  *                                    -----
53  * Please refer to SF-108797-SW for a general overview of the TLV partition
56  *                                    -----
62  *   -  L is a location, indicating where this tag is expected to be found:
69  *   -  TTT is a type, which is just a unique value.  The same type value
73  *   -  NNNN is an index of some form.  Some item types are per-port, some
74  *      are per-PF, some are per-partition-type.
76  *                                    -----
89 /* ----------------------------------------------------------------------------
90  *  General structure (defined by SF-108797-SW)
91  * ----------------------------------------------------------------------------
121  * are for RFID-selectable presets that should immediately follow the default segment.
160 /* ----------------------------------------------------------------------------
162  * ----------------------------------------------------------------------------
176 /* Siena-style per-port MAC address allocation.
179  * by adding <stride> to the low-order byte(s).
185 #define TLV_TAG_PORT_MAC(port)          (0x00020000 + (port))  argument
200  * global and per-pf TLVs for this, the global TLV is new for Medford and is
201  * used in preference to the per-pf TLV.
223  * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs
225  * per-pf TLV.
247  * the device is allowed to enumerate. There are global and per-pf TLVs for
249  * per-pf TLV.
325 #define TLV_MAX_PF_DEFAULT (-1)                 /* Use FW default for largest PF RID  */
329 /* Per-PF configuration. Note that not all these fields are necessarily useful
352  * that can be set through the MC command-line other than the PCIe
354 #define TLV_TAG_TMP_GUBBINS (0x10090000)        /* legacy symbol - do not use */
371   uint32_t dut_features;        /* All 1s -> leave alone */
372   int8_t with_rmon;             /* 0 -> off, 1 -> on, -1 -> leave alone */
374   int8_t clk_mode;             /* 0 -> off, 1 -> on, -1 -> leave alone */
376   int8_t rx_dc_size;           /* -1 -> leave alone */
381 /* Global port configuration
383  * This is now deprecated in favour of a platform-provided default
397  * This is intended for user-configurable selection of optional firmware
453 #define TLV_TAG_CLOCK_CONFIG       (0x000d0000) /* legacy symbol - do not use */
478 /* EF10-style global pool of MAC addresses.
496 #define TLV_TAG_ATB_0V9_TARGET     (0x000f0000) /* legacy symbol - do not use */
499 /* The target value for the 0v9 power rail measured on-chip at the
520  * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
535 /* Dynamic port mode.
537  * Allows selecting alternate port configuration for platforms that support it
539  * number of externally visible ports (and, hence, PF to port mapping), so must
542  * Port mode naming convention is
546  * Port lane width determines the capabilities (speeds) of the ports, subject
549  *  - single lane ports can do 25G/10G/1G
550  *  - dual lane ports can do 50G/25G/10G/1G (with fallback to 1 lane)
551  *  - quad lane ports can do 100G/40G/50G/25G/10G/1G (with fallback to 2 or 1 lanes)
564 /* Huntington port modes */
573 /* Medford (and later) port modes */
594 /* Snapper-only Medford2 port modes.
596  * selection between multi-channel and LLPCS. In production,
600 …E_2x1_2x1_LL                 (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */
601 #define TLV_PORT_MODE_4x1_NA_LL                  (20) /* Quad 10G/25G on mdi0, low-latency PCS */
602 #define TLV_PORT_MODE_NA_4x1_LL                  (21) /* Quad 10G/25G on mdi1, low-latency PCS */
603 #define TLV_PORT_MODE_1x1_NA_LL                  (23) /* Single 10G/25G on mdi0, low-latency PCS */
604 …1_1x1_LL                 (24) /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */
608 /* Deprecated Medford aliases - DO NOT USE IN NEW CODE */
617 /* Type of the v-switch created implicitly by the firmware */
619 #define TLV_TAG_VSWITCH_TYPE(port)       (0x10120000 + (port))  argument
625 …E_DEFAULT        (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
634 /* A VLAN tag for the v-port created implicitly by the firmware */
656 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per…
662 #define TLV_TAG_PRIVILEGE_MASK          (0x10150000) /* legacy symbol - do not use */
664 struct tlv_privilege_mask {                          /* legacy structure - do not use */
711 #define TLV_TAG_PFIOV(port)             (0x10170000 + (port))  argument
725  * will steal traffic from MAC multicast filters on a per-function basis.
736  * This option is intended to provide run-time control over this feature
752 /* Pacer rate limit per PF */
790  * away from the highest numbered port first, so a vi_count of 1024 means 1024
791  * VIs on the first port and 0 on the second (on a Torino).
818 #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
843 #define TLV_TX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
881   uint32_t port;  member
903   uint32_t port[TLV_MAX_TSACS];  member
982 #define TLV_BIU_VI_WINDOW_MODE_8K    0  /*  8k per VI, CTPIO not mapped, medford/hunt compatible */
983 #define TLV_BIU_VI_WINDOW_MODE_16K   1  /* 16k per VI, CTPIO mapped */
984 #define TLV_BIU_VI_WINDOW_MODE_64K   2  /* 64k per VI, CTPIO mapped, POWER-friendly */
991 #define TLV_TAG_FASTPD_MODE(port)       (0x10290000 + (port))  argument
1001 /* L3xUDP datapath firmware UDP port configuration