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16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
53 * Please refer to SF-108797-SW for a general overview of the TLV partition
58 * The current tag IDs have a general structure: with the exception of the
62 * - L is a location, indicating where this tag is expected to be found:
69 * - TTT is a type, which is just a unique value. The same type value
70 * might appear in both locations, indicating a relationship between
110 * In a TLV partition, this must be the first item in the sequence, at offset
122 * The default segment may also have preset > 0, which means that it is a preset
131 * In a TLV partition, this must be the last item in the sequence, immediately
181 * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool
199 * expected to change. It is formatted as a standard PCI VPD block. There are
223 * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs
246 * This is a set of edits made to the default PCI config space values before
278 * A subtype may optionally be stored for each type of partition present in
279 * the NVRAM. For example, this may be used to allow a generic firmware update
280 * utility to select a specific variant of firmware for a specific variant of
298 * A version may optionally be stored for each type of partition present in
299 * the NVRAM. This provides a standard way of tracking the currently stored
326 #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */
351 /* Development ONLY. This is a single TLV tag for all the gubbins
353 * settings. This is a temporary measure. */
383 * This is now deprecated in favour of a platform-provided default
519 * by a bitmap rather than having the number of the highest visible one. As such
520 * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
547 * to architecture capabilities (e.g. 25G support) and switch bandwidth
549 * - single lane ports can do 25G/10G/1G
550 * - dual lane ports can do 50G/25G/10G/1G (with fallback to 1 lane)
551 * - quad lane ports can do 100G/40G/50G/25G/10G/1G (with fallback to 2 or 1 lanes)
574 #define TLV_PORT_MODE_1x1_NA (0) /* Single 10G/25G on mdi0 */
579 #define TLV_PORT_MODE_1x1_1x1 (2) /* Single 10G/25G on mdi0, single 10G/25G on m…
581 #define TLV_PORT_MODE_2x1_2x1 (5) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 …
582 #define TLV_PORT_MODE_4x1_NA (4) /* Quad 10G/25G on mdi0 */
583 #define TLV_PORT_MODE_NA_4x1 (8) /* Quad 10G/25G on mdi1 */
584 #define TLV_PORT_MODE_1x4_2x1 (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */
585 #define TLV_PORT_MODE_2x1_1x4 (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */
591 #define TLV_PORT_MODE_1x2_2x1 (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */
592 #define TLV_PORT_MODE_2x1_1x2 (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */
600 #define TLV_PORT_MODE_2x1_2x1_LL (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1…
601 #define TLV_PORT_MODE_4x1_NA_LL (20) /* Quad 10G/25G on mdi0, low-latency PCS */
602 #define TLV_PORT_MODE_NA_4x1_LL (21) /* Quad 10G/25G on mdi1, low-latency PCS */
603 #define TLV_PORT_MODE_1x1_NA_LL (23) /* Single 10G/25G on mdi0, low-latency PCS */
604 #define TLV_PORT_MODE_1x1_1x1_LL (24) /* Single 10G/25G on mdi0, single 10G/25G on …
625 …E_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
634 /* A VLAN tag for the v-port created implicitly by the firmware */
642 …PORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */
656 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per…
697 /* Additional privileges given to a selected PF.
725 * will steal traffic from MAC multicast filters on a per-function basis.
763 * This setting allows OCSD to be disabled. This is a requirement for HP
788 * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also
790 * away from the highest numbered port first, so a vi_count of 1024 means 1024
791 * VIs on the first port and 0 on the second (on a Torino).
865 * be moved to a private partition during TSA development. It is not used in any
891 * be moved to a private partition during TSA development. It is not used in any
912 * be moved to a private partition during TSA development. It is not used in any
929 * be moved to a private partition during TSA development. It is not used in any
947 * be moved to a private partition during TSA development. It is not used in any