Lines Matching +full:10 +full:g

71  *      the items (e.g. static and dynamic VPD below).
222  * This is the portion of VPD which may be changed (e.g. by firmware updates).
538  * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the
547  * to architecture capabilities (e.g. 25G support) and switch bandwidth
549  *  - single lane ports can do 25G/10G/1G
550  *  - dual lane ports can do 50G/25G/10G/1G (with fallback to 1 lane)
551  *  - quad lane ports can do 100G/40G/50G/25G/10G/1G (with fallback to 2 or 1 lanes)
574 #define TLV_PORT_MODE_1x1_NA                     (0) /* Single 10G/25G on mdi0 */
575 #define TLV_PORT_MODE_1x4_NA                     (1) /* Single 100G/40G on mdi0 */
576 #define TLV_PORT_MODE_NA_1x4                     (22) /* Single 100G/40G on mdi1 */
577 #define TLV_PORT_MODE_1x2_NA                     (10) /* Single 50G on mdi0 */
578 #define TLV_PORT_MODE_NA_1x2                     (11) /* Single 50G on mdi1 */
579 #define TLV_PORT_MODE_1x1_1x1                    (2) /* Single 10G/25G on mdi0, single 10G/25G on m…
580 #define TLV_PORT_MODE_1x4_1x4                    (3) /* Single 40G on mdi0, single 40G on mdi1 */
581 #define TLV_PORT_MODE_2x1_2x1                    (5) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 …
582 #define TLV_PORT_MODE_4x1_NA                     (4) /* Quad 10G/25G on mdi0 */
583 #define TLV_PORT_MODE_NA_4x1                     (8) /* Quad 10G/25G on mdi1 */
584 #define TLV_PORT_MODE_1x4_2x1                    (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */
585 #define TLV_PORT_MODE_2x1_1x4                    (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */
586 #define TLV_PORT_MODE_1x2_1x2                    (12) /* Single 50G on mdi0, single 50G on mdi1 */
587 #define TLV_PORT_MODE_2x2_NA                     (13) /* Dual 50G on mdi0 */
588 #define TLV_PORT_MODE_NA_2x2                     (14) /* Dual 50G on mdi1 */
589 #define TLV_PORT_MODE_1x4_1x2                    (15) /* Single 40G on mdi0, single 50G on mdi1 */
590 #define TLV_PORT_MODE_1x2_1x4                    (16) /* Single 50G on mdi0, single 40G on mdi1 */
591 #define TLV_PORT_MODE_1x2_2x1                    (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */
592 #define TLV_PORT_MODE_2x1_1x2                    (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */
600 #define TLV_PORT_MODE_2x1_2x1_LL                 (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1…
601 #define TLV_PORT_MODE_4x1_NA_LL                  (20) /* Quad 10G/25G on mdi0, low-latency PCS */
602 #define TLV_PORT_MODE_NA_4x1_LL                  (21) /* Quad 10G/25G on mdi1, low-latency PCS */
603 #define TLV_PORT_MODE_1x1_NA_LL                  (23) /* Single 10G/25G on mdi0, low-latency PCS */
604 #define TLV_PORT_MODE_1x1_1x1_LL                 (24) /* Single 10G/25G on mdi0, single 10G/25G on …