Lines Matching +full:port +full:- +full:mapping

1 /*-
2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
52 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || in efx_mcdi_get_port_assignment()
53 enp->en_family == EFX_FAMILY_MEDFORD || in efx_mcdi_get_port_assignment()
54 enp->en_family == EFX_FAMILY_MEDFORD2); in efx_mcdi_get_port_assignment()
98 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || in efx_mcdi_get_port_modes()
99 enp->en_family == EFX_FAMILY_MEDFORD || in efx_mcdi_get_port_modes()
100 enp->en_family == EFX_FAMILY_MEDFORD2); in efx_mcdi_get_port_modes()
161 efx_port_t *epp = &(enp->en_port); in ef10_nic_get_port_mode_bandwidth()
171 /* No port mode info available. */ in ef10_nic_get_port_mode_bandwidth()
175 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_25000FDX)) in ef10_nic_get_port_mode_bandwidth()
180 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_50000FDX)) in ef10_nic_get_port_mode_bandwidth()
185 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_100000FDX)) in ef10_nic_get_port_mode_bandwidth()
215 /* Legacy Medford-only mode. Do not use (see bug63270) */ in ef10_nic_get_port_mode_bandwidth()
265 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL); in efx_mcdi_vadaptor_alloc()
276 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0); in efx_mcdi_vadaptor_alloc()
336 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
337 enp->en_family == EFX_FAMILY_MEDFORD ||
338 enp->en_family == EFX_FAMILY_MEDFORD2);
394 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
395 enp->en_family == EFX_FAMILY_MEDFORD ||
396 enp->en_family == EFX_FAMILY_MEDFORD2);
458 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || in efx_mcdi_get_clock()
459 enp->en_family == EFX_FAMILY_MEDFORD || in efx_mcdi_get_clock()
460 enp->en_family == EFX_FAMILY_MEDFORD2); in efx_mcdi_get_clock()
859 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle)); in ef10_nic_alloc_piobufs()
861 enp->en_arch.ef10.ena_piobuf_count = 0; in ef10_nic_alloc_piobufs()
864 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i]; in ef10_nic_alloc_piobufs()
869 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0; in ef10_nic_alloc_piobufs()
870 enp->en_arch.ef10.ena_piobuf_count++; in ef10_nic_alloc_piobufs()
876 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) { in ef10_nic_alloc_piobufs()
877 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i]; in ef10_nic_alloc_piobufs()
882 enp->en_arch.ef10.ena_piobuf_count = 0; in ef10_nic_alloc_piobufs()
892 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) { in ef10_nic_free_piobufs()
893 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i]; in ef10_nic_free_piobufs()
898 enp->en_arch.ef10.ena_piobuf_count = 0; in ef10_nic_free_piobufs()
901 /* Sub-allocate a block from a piobuf */
911 efx_nic_cfg_t *encp = &enp->en_nic_cfg; in ef10_nic_pio_alloc()
912 efx_drv_cfg_t *edcp = &enp->en_drv_cfg; in ef10_nic_pio_alloc()
917 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || in ef10_nic_pio_alloc()
918 enp->en_family == EFX_FAMILY_MEDFORD || in ef10_nic_pio_alloc()
919 enp->en_family == EFX_FAMILY_MEDFORD2); in ef10_nic_pio_alloc()
926 if ((edcp->edc_pio_alloc_size == 0) || in ef10_nic_pio_alloc()
927 (enp->en_arch.ef10.ena_piobuf_count == 0)) { in ef10_nic_pio_alloc()
931 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size; in ef10_nic_pio_alloc()
933 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) { in ef10_nic_pio_alloc()
934 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf]; in ef10_nic_pio_alloc()
951 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf]; in ef10_nic_pio_alloc()
954 *sizep = edcp->edc_pio_alloc_size; in ef10_nic_pio_alloc()
967 /* Free a piobuf sub-allocated block */
977 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) || in ef10_nic_pio_free()
983 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum]; in ef10_nic_pio_free()
1064 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_get_datapath_caps()
1070 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0) in ef10_get_datapath_caps()
1108 encp->enc_rx_prefix_size = 14; in ef10_get_datapath_caps()
1113 encp->enc_rx_scale_additional_modes_supported = B_TRUE; in ef10_get_datapath_caps()
1115 encp->enc_rx_scale_additional_modes_supported = B_FALSE; in ef10_get_datapath_caps()
1120 encp->enc_fw_assisted_tso_enabled = B_TRUE; in ef10_get_datapath_caps()
1122 encp->enc_fw_assisted_tso_enabled = B_FALSE; in ef10_get_datapath_caps()
1126 encp->enc_fw_assisted_tso_v2_enabled = B_TRUE; in ef10_get_datapath_caps()
1127 encp->enc_fw_assisted_tso_v2_n_contexts = MCDI_OUT_WORD(req, in ef10_get_datapath_caps()
1130 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE; in ef10_get_datapath_caps()
1131 encp->enc_fw_assisted_tso_v2_n_contexts = 0; in ef10_get_datapath_caps()
1136 encp->enc_fw_assisted_tso_v2_encap_enabled = B_TRUE; in ef10_get_datapath_caps()
1138 encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE; in ef10_get_datapath_caps()
1142 encp->enc_datapath_cap_evb = B_TRUE; in ef10_get_datapath_caps()
1144 encp->enc_datapath_cap_evb = B_FALSE; in ef10_get_datapath_caps()
1148 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE; in ef10_get_datapath_caps()
1150 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE; in ef10_get_datapath_caps()
1154 encp->enc_rx_batching_enabled = B_TRUE; in ef10_get_datapath_caps()
1156 encp->enc_rx_batching_enabled = B_FALSE; in ef10_get_datapath_caps()
1162 encp->enc_rx_batch_max = 16; in ef10_get_datapath_caps()
1166 encp->enc_rx_disable_scatter_supported = B_TRUE; in ef10_get_datapath_caps()
1168 encp->enc_rx_disable_scatter_supported = B_FALSE; in ef10_get_datapath_caps()
1172 encp->enc_rx_packed_stream_supported = B_TRUE; in ef10_get_datapath_caps()
1174 encp->enc_rx_packed_stream_supported = B_FALSE; in ef10_get_datapath_caps()
1181 encp->enc_rx_var_packed_stream_supported = B_TRUE; in ef10_get_datapath_caps()
1183 encp->enc_rx_var_packed_stream_supported = B_FALSE; in ef10_get_datapath_caps()
1185 /* Check if the firmware supports equal stride super-buffer mode */ in ef10_get_datapath_caps()
1187 encp->enc_rx_es_super_buffer_supported = B_TRUE; in ef10_get_datapath_caps()
1189 encp->enc_rx_es_super_buffer_supported = B_FALSE; in ef10_get_datapath_caps()
1193 encp->enc_fw_subvariant_no_tx_csum_supported = B_TRUE; in ef10_get_datapath_caps()
1195 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE; in ef10_get_datapath_caps()
1199 encp->enc_allow_set_mac_with_installed_filters = B_TRUE; in ef10_get_datapath_caps()
1201 encp->enc_allow_set_mac_with_installed_filters = B_FALSE; in ef10_get_datapath_caps()
1208 encp->enc_enhanced_set_mac_supported = B_TRUE; in ef10_get_datapath_caps()
1210 encp->enc_enhanced_set_mac_supported = B_FALSE; in ef10_get_datapath_caps()
1217 encp->enc_init_evq_v2_supported = B_TRUE; in ef10_get_datapath_caps()
1219 encp->enc_init_evq_v2_supported = B_FALSE; in ef10_get_datapath_caps()
1222 * Check if firmware-verified NVRAM updates must be used. in ef10_get_datapath_caps()
1230 encp->enc_nvram_update_verify_result_supported = B_TRUE; in ef10_get_datapath_caps()
1232 encp->enc_nvram_update_verify_result_supported = B_FALSE; in ef10_get_datapath_caps()
1239 encp->enc_pm_and_rxdp_counters = B_TRUE; in ef10_get_datapath_caps()
1241 encp->enc_pm_and_rxdp_counters = B_FALSE; in ef10_get_datapath_caps()
1248 encp->enc_mac_stats_40g_tx_size_bins = B_TRUE; in ef10_get_datapath_caps()
1250 encp->enc_mac_stats_40g_tx_size_bins = B_FALSE; in ef10_get_datapath_caps()
1257 encp->enc_tunnel_encapsulations_supported = in ef10_get_datapath_caps()
1264 encp->enc_tunnel_config_udp_entries_max = in ef10_get_datapath_caps()
1267 encp->enc_tunnel_config_udp_entries_max = 0; in ef10_get_datapath_caps()
1281 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; in ef10_get_datapath_caps()
1284 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_16K; in ef10_get_datapath_caps()
1287 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_64K; in ef10_get_datapath_caps()
1290 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID; in ef10_get_datapath_caps()
1293 } else if ((enp->en_family == EFX_FAMILY_HUNTINGTON) || in ef10_get_datapath_caps()
1294 (enp->en_family == EFX_FAMILY_MEDFORD)) { in ef10_get_datapath_caps()
1296 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; in ef10_get_datapath_caps()
1298 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID; in ef10_get_datapath_caps()
1304 encp->enc_mac_stats_nstats = MCDI_OUT_WORD(req, in ef10_get_datapath_caps()
1307 /* Use Siena-compatible legacy MAC stats */ in ef10_get_datapath_caps()
1308 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS; in ef10_get_datapath_caps()
1311 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V2) in ef10_get_datapath_caps()
1312 encp->enc_fec_counters = B_TRUE; in ef10_get_datapath_caps()
1314 encp->enc_fec_counters = B_FALSE; in ef10_get_datapath_caps()
1316 /* Check if the firmware provides head-of-line blocking counters */ in ef10_get_datapath_caps()
1318 encp->enc_hlb_counters = B_TRUE; in ef10_get_datapath_caps()
1320 encp->enc_hlb_counters = B_FALSE; in ef10_get_datapath_caps()
1324 /* Only one exclusive RSS context is available per port. */ in ef10_get_datapath_caps()
1325 encp->enc_rx_scale_max_exclusive_contexts = 1; in ef10_get_datapath_caps()
1327 switch (enp->en_family) { in ef10_get_datapath_caps()
1329 encp->enc_rx_scale_hash_alg_mask = in ef10_get_datapath_caps()
1337 * non-standard algorithm for hash computation. in ef10_get_datapath_caps()
1343 encp->enc_rx_scale_hash_alg_mask = in ef10_get_datapath_caps()
1352 /* Port numbers cannot contribute to the hash value */ in ef10_get_datapath_caps()
1353 encp->enc_rx_scale_l4_hash_supported = B_FALSE; in ef10_get_datapath_caps()
1361 encp->enc_rx_scale_max_exclusive_contexts = 64 - 6; in ef10_get_datapath_caps()
1363 encp->enc_rx_scale_hash_alg_mask = in ef10_get_datapath_caps()
1367 * It is possible to use port numbers as in ef10_get_datapath_caps()
1370 encp->enc_rx_scale_l4_hash_supported = B_TRUE; in ef10_get_datapath_caps()
1376 encp->enc_filter_action_flag_supported = B_TRUE; in ef10_get_datapath_caps()
1378 encp->enc_filter_action_flag_supported = B_FALSE; in ef10_get_datapath_caps()
1381 encp->enc_filter_action_mark_supported = B_TRUE; in ef10_get_datapath_caps()
1383 encp->enc_filter_action_mark_supported = B_FALSE; in ef10_get_datapath_caps()
1387 encp->enc_filter_action_mark_max = MCDI_OUT_DWORD(req, in ef10_get_datapath_caps()
1390 encp->enc_filter_action_mark_max = 0; in ef10_get_datapath_caps()
1433 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_get_privilege_mask()
1437 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf, in ef10_get_privilege_mask()
1466 * Table of mapping schemes from port number to external number.
1468 * Each port number ultimately corresponds to a connector: either as part of
1470 * the board, or fixed to the board (e.g. 10GBASE-T magjack on SFN5121T
1473 * Port number (0-based)
1475 * port mapping (n:1)
1478 * External port number (1-based)
1487 * how to determine which external cage/magjack corresponds to the port
1490 * The count of consecutive port numbers that map to each external number,
1491 * is determined by the chip family and the current port mode.
1493 * For the Huntington family, the current port mode cannot be discovered,
1494 * but a single mapping is used by all modes for a given chip variant,
1495 * so the mapping used is instead the last match in the table to the full
1496 * set of port modes to which the NIC can be configured. Therefore the
1497 * ordering of entries in the mapping table is significant.
1505 * Modes used by Huntington family controllers where each port
1508 * port 0 -> cage 1
1509 * port 1 -> cage 2
1511 * port 0 -> cage 1
1512 * port 1 -> cage 2
1513 * port 2 -> cage 3
1514 * port 3 -> cage 4
1525 * adjacent port numbers map to each cage.
1527 * port 0 -> cage 1
1528 * port 1 -> cage 1
1529 * port 2 -> cage 2
1530 * port 3 -> cage 2
1541 * Modes that on Medford allocate each port number to a separate
1543 * port 0 -> cage 1
1544 * port 1 -> cage 2
1545 * port 2 -> cage 3
1546 * port 3 -> cage 4
1555 * Modes that on Medford allocate 2 adjacent port numbers to each
1557 * port 0 -> cage 1
1558 * port 1 -> cage 1
1559 * port 2 -> cage 2
1560 * port 3 -> cage 2
1573 * Modes that on Medford allocate 4 adjacent port numbers to each
1575 * port 0 -> cage 1
1576 * port 1 -> cage 1
1577 * port 2 -> cage 1
1578 * port 3 -> cage 1
1588 * Modes that on Medford allocate 4 adjacent port numbers to each
1590 * port 0 -> cage 2
1591 * port 1 -> cage 2
1592 * port 2 -> cage 2
1593 * port 3 -> cage 2
1601 * Modes that on Medford2 allocate each port number to a separate
1603 * port 0 -> cage 1
1604 * port 1 -> cage 2
1605 * port 2 -> cage 3
1606 * port 3 -> cage 4
1620 * Modes that on Medford2 allocate 1 port to cage 1 and the rest
1622 * port 0 -> cage 1
1623 * port 1 -> cage 2
1624 * port 2 -> cage 2
1633 * Modes that on Medford2 allocate 2 adjacent port numbers to each
1635 * port 0 -> cage 1
1636 * port 1 -> cage 1
1637 * port 2 -> cage 2
1638 * port 3 -> cage 2
1651 * Modes that on Medford2 allocate 2 adjacent port numbers to each
1653 * port 0 -> cage 2
1654 * port 1 -> cage 2
1662 * Modes that on Medford2 allocate 4 adjacent port numbers to each
1664 * port 0 -> cage 1
1665 * port 1 -> cage 1
1666 * port 2 -> cage 1
1667 * port 3 -> cage 1
1675 * Modes that on Medford2 allocate 4 adjacent port numbers to each
1677 * port 0 -> cage 2
1678 * port 1 -> cage 2
1679 * port 2 -> cage 2
1680 * port 3 -> cage 2
1693 __in uint32_t port, in ef10_external_port_mapping() argument
1702 int ext_index = port; /* Default 1-1 mapping */ in ef10_external_port_mapping()
1707 * No current port mode information (i.e. Huntington) in ef10_external_port_mapping()
1708 * - infer mapping from available modes in ef10_external_port_mapping()
1713 * No port mode information available in ef10_external_port_mapping()
1714 * - use default mapping in ef10_external_port_mapping()
1724 * Infer the internal port -> external number mapping from in ef10_external_port_mapping()
1725 * the possible port modes for this NIC. in ef10_external_port_mapping()
1730 if (eepmp->family != enp->en_family) in ef10_external_port_mapping()
1732 matches = (eepmp->modes_mask & port_modes); in ef10_external_port_mapping()
1736 * there will be multiple matches. The mapping on the in ef10_external_port_mapping()
1754 * port numbers, so find the one with the closest base_port. in ef10_external_port_mapping()
1759 uint32_t base = mapp->base_port[i]; in ef10_external_port_mapping()
1760 if ((base != EFX_EXT_PORT_NA) && (base <= port)) { in ef10_external_port_mapping()
1761 if ((port - base) < delta) { in ef10_external_port_mapping()
1762 delta = (port - base); in ef10_external_port_mapping()
1782 const efx_nic_ops_t *enop = enp->en_enop; in ef10_nic_board_cfg()
1783 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); in ef10_nic_board_cfg()
1784 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_nic_board_cfg()
1786 efx_port_t *epp = &(enp->en_port); in ef10_nic_board_cfg()
1789 uint32_t port; in ef10_nic_board_cfg() local
1796 /* Get the (zero-based) MCDI port number */ in ef10_nic_board_cfg()
1797 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0) in ef10_nic_board_cfg()
1800 /* EFX MCDI interface uses one-based port numbers */ in ef10_nic_board_cfg()
1801 emip->emi_port = port + 1; in ef10_nic_board_cfg()
1803 if ((rc = ef10_external_port_mapping(enp, port, in ef10_nic_board_cfg()
1804 &encp->enc_external_port)) != 0) in ef10_nic_board_cfg()
1809 * per-function privilege and dynamic config info). in ef10_nic_board_cfg()
1810 * - PCIe PF: pf = PF number, vf = 0xffff. in ef10_nic_board_cfg()
1811 * - PCIe VF: pf = parent PF, vf = VF number. in ef10_nic_board_cfg()
1816 encp->enc_pf = pf; in ef10_nic_board_cfg()
1817 encp->enc_vf = vf; in ef10_nic_board_cfg()
1845 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); in ef10_nic_board_cfg()
1857 encp->enc_board_type = board_type; in ef10_nic_board_cfg()
1858 encp->enc_clk_mult = 1; /* not used for EF10 */ in ef10_nic_board_cfg()
1860 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ in ef10_nic_board_cfg()
1869 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_BASER_FEC)) in ef10_nic_board_cfg()
1870 epp->ep_phy_cap_mask |= in ef10_nic_board_cfg()
1872 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_RS_FEC)) in ef10_nic_board_cfg()
1873 epp->ep_phy_cap_mask |= in ef10_nic_board_cfg()
1875 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_25G_BASER_FEC)) in ef10_nic_board_cfg()
1876 epp->ep_phy_cap_mask |= in ef10_nic_board_cfg()
1882 epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask; in ef10_nic_board_cfg()
1883 epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask; in ef10_nic_board_cfg()
1890 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN; in ef10_nic_board_cfg()
1892 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); in ef10_nic_board_cfg()
1894 encp->enc_tx_dma_desc_boundary = 0; in ef10_nic_board_cfg()
1900 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; in ef10_nic_board_cfg()
1908 encp->enc_evq_limit = 1024; in ef10_nic_board_cfg()
1909 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET; in ef10_nic_board_cfg()
1910 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET; in ef10_nic_board_cfg()
1912 encp->enc_buftbl_limit = 0xFFFFFFFF; in ef10_nic_board_cfg()
1923 encp->enc_intr_vec_base = base; in ef10_nic_board_cfg()
1924 encp->enc_intr_limit = nvec; in ef10_nic_board_cfg()
1930 * can result in time-of-check/time-of-use bugs. in ef10_nic_board_cfg()
1934 encp->enc_privilege_mask = mask; in ef10_nic_board_cfg()
1936 /* Get remaining controller-specific board config */ in ef10_nic_board_cfg()
1937 if ((rc = enop->eno_board_cfg(enp)) != 0) in ef10_nic_board_cfg()
1973 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_nic_probe()
1974 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg); in ef10_nic_probe()
1977 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || in ef10_nic_probe()
1978 enp->en_family == EFX_FAMILY_MEDFORD || in ef10_nic_probe()
1979 enp->en_family == EFX_FAMILY_MEDFORD2); in ef10_nic_probe()
2001 * port. in ef10_nic_probe()
2003 edcp->edc_min_vi_count = edcp->edc_max_vi_count = in ef10_nic_probe()
2004 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit)); in ef10_nic_probe()
2007 edcp->edc_max_piobuf_count = 0; in ef10_nic_probe()
2008 edcp->edc_pio_alloc_size = 0; in ef10_nic_probe()
2029 encp->enc_features = enp->en_features; in ef10_nic_probe()
2062 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_nic_set_drv_limits()
2063 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg); in ef10_nic_set_drv_limits()
2075 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit); in ef10_nic_set_drv_limits()
2076 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit); in ef10_nic_set_drv_limits()
2077 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit); in ef10_nic_set_drv_limits()
2079 edcp->edc_min_vi_count = in ef10_nic_set_drv_limits()
2082 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit); in ef10_nic_set_drv_limits()
2083 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit); in ef10_nic_set_drv_limits()
2084 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit); in ef10_nic_set_drv_limits()
2086 edcp->edc_max_vi_count = in ef10_nic_set_drv_limits()
2090 * Check limits for sub-allocated piobuf blocks. in ef10_nic_set_drv_limits()
2093 if ((encp->enc_piobuf_size == 0) || in ef10_nic_set_drv_limits()
2094 (encp->enc_piobuf_limit == 0) || in ef10_nic_set_drv_limits()
2095 (edlp->edl_min_pio_alloc_size == 0) || in ef10_nic_set_drv_limits()
2096 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) { in ef10_nic_set_drv_limits()
2098 edcp->edc_max_piobuf_count = 0; in ef10_nic_set_drv_limits()
2099 edcp->edc_pio_alloc_size = 0; in ef10_nic_set_drv_limits()
2104 MAX(edlp->edl_min_pio_alloc_size, in ef10_nic_set_drv_limits()
2105 encp->enc_piobuf_min_alloc_size); in ef10_nic_set_drv_limits()
2107 blks_per_piobuf = encp->enc_piobuf_size / blk_size; in ef10_nic_set_drv_limits()
2110 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf); in ef10_nic_set_drv_limits()
2113 if ((edlp->edl_max_pio_alloc_count > 0) && in ef10_nic_set_drv_limits()
2114 (edlp->edl_max_pio_alloc_count < blk_count)) { in ef10_nic_set_drv_limits()
2115 blk_count = edlp->edl_max_pio_alloc_count; in ef10_nic_set_drv_limits()
2118 edcp->edc_pio_alloc_size = blk_size; in ef10_nic_set_drv_limits()
2119 edcp->edc_max_piobuf_count = in ef10_nic_set_drv_limits()
2120 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf; in ef10_nic_set_drv_limits()
2163 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR); in ef10_nic_reset()
2181 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg); in ef10_nic_init()
2190 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || in ef10_nic_init()
2191 enp->en_family == EFX_FAMILY_MEDFORD || in ef10_nic_init()
2192 enp->en_family == EFX_FAMILY_MEDFORD2); in ef10_nic_init()
2198 /* Allocate (optional) on-chip PIO buffers */ in ef10_nic_init()
2199 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count); in ef10_nic_init()
2202 * For best performance, PIO writes should use a write-combined in ef10_nic_init()
2203 * (WC) memory mapping. Using a separate WC mapping for the PIO in ef10_nic_init()
2207 * To avoid this we use a single uncached (UC) mapping for VI in ef10_nic_init()
2208 * register access, and a single WC mapping for extra VIs used in ef10_nic_init()
2211 * Each piobuf must be linked to a VI in the WC mapping, and to in ef10_nic_init()
2212 * each VI that is using a sub-allocated block from the piobuf. in ef10_nic_init()
2214 min_vi_count = edcp->edc_min_vi_count; in ef10_nic_init()
2216 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count; in ef10_nic_init()
2238 enp->en_arch.ef10.ena_vi_base = vi_base; in ef10_nic_init()
2239 enp->en_arch.ef10.ena_vi_count = vi_count; in ef10_nic_init()
2240 enp->en_arch.ef10.ena_vi_shift = vi_shift; in ef10_nic_init()
2242 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) { in ef10_nic_init()
2247 enp->en_arch.ef10.ena_pio_write_vi_base = in ef10_nic_init()
2248 vi_count - enp->en_arch.ef10.ena_piobuf_count; in ef10_nic_init()
2250 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=, in ef10_nic_init()
2252 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=, in ef10_nic_init()
2254 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift; in ef10_nic_init()
2256 /* Save UC memory mapping details */ in ef10_nic_init()
2257 enp->en_arch.ef10.ena_uc_mem_map_offset = 0; in ef10_nic_init()
2258 if (enp->en_arch.ef10.ena_piobuf_count > 0) { in ef10_nic_init()
2259 enp->en_arch.ef10.ena_uc_mem_map_size = in ef10_nic_init()
2261 enp->en_arch.ef10.ena_pio_write_vi_base); in ef10_nic_init()
2263 enp->en_arch.ef10.ena_uc_mem_map_size = in ef10_nic_init()
2265 enp->en_arch.ef10.ena_vi_count); in ef10_nic_init()
2268 /* Save WC memory mapping details */ in ef10_nic_init()
2269 enp->en_arch.ef10.ena_wc_mem_map_offset = in ef10_nic_init()
2270 enp->en_arch.ef10.ena_uc_mem_map_offset + in ef10_nic_init()
2271 enp->en_arch.ef10.ena_uc_mem_map_size; in ef10_nic_init()
2273 enp->en_arch.ef10.ena_wc_mem_map_size = in ef10_nic_init()
2275 enp->en_arch.ef10.ena_piobuf_count); in ef10_nic_init()
2277 /* Link piobufs to extra VIs in WC mapping */ in ef10_nic_init()
2278 if (enp->en_arch.ef10.ena_piobuf_count > 0) { in ef10_nic_init()
2279 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) { in ef10_nic_init()
2281 enp->en_arch.ef10.ena_pio_write_vi_base + i, in ef10_nic_init()
2282 enp->en_arch.ef10.ena_piobuf_handle[i]); in ef10_nic_init()
2292 * driver has yet to bring up the EVB port. See bug 56147. In this case, in ef10_nic_init()
2302 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) || in ef10_nic_init()
2324 enp->en_vport_id = EVB_PORT_ID_ASSIGNED; in ef10_nic_init()
2325 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2; in ef10_nic_init()
2353 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || in ef10_nic_get_vi_pool()
2354 enp->en_family == EFX_FAMILY_MEDFORD || in ef10_nic_get_vi_pool()
2355 enp->en_family == EFX_FAMILY_MEDFORD2); in ef10_nic_get_vi_pool()
2361 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base; in ef10_nic_get_vi_pool()
2375 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || in ef10_nic_get_bar_region()
2376 enp->en_family == EFX_FAMILY_MEDFORD || in ef10_nic_get_bar_region()
2377 enp->en_family == EFX_FAMILY_MEDFORD2); in ef10_nic_get_bar_region()
2380 * TODO: Specify host memory mapping alignment and granularity in ef10_nic_get_bar_region()
2387 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset; in ef10_nic_get_bar_region()
2388 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size; in ef10_nic_get_bar_region()
2393 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset; in ef10_nic_get_bar_region()
2394 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size; in ef10_nic_get_bar_region()
2416 if (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL) in ef10_nic_hw_unavailable()
2436 enp->en_reset_flags |= EFX_RESET_HW_UNAVAIL; in ef10_nic_set_hw_unavailable()
2446 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id); in ef10_nic_fini()
2447 enp->en_vport_id = 0; in ef10_nic_fini()
2449 /* Unlink piobufs from extra VIs in WC mapping */ in ef10_nic_fini()
2450 if (enp->en_arch.ef10.ena_piobuf_count > 0) { in ef10_nic_fini()
2451 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) { in ef10_nic_fini()
2453 enp->en_arch.ef10.ena_pio_write_vi_base + i); in ef10_nic_fini()
2462 enp->en_arch.ef10.ena_vi_count = 0; in ef10_nic_fini()