Lines Matching +full:0 +full:x1020
33 * simultaneously active holding 96 descriptors. Each descriptor can use 0 or
47 #define SEC_20_ID 0x0000000000000040ULL
48 #define SEC_30_ID 0x0030030000000000ULL
49 #define SEC_31_ID 0x0030030100000000ULL
52 #define SEC_MAX_DMA_BLOCK_SIZE 0xFFFF
283 } while (0)
287 for (i = 0; i < SEC_POINTERS; i++) \
289 } while (0)
293 for (i = 0; i < SEC_POINTERS; i++) \
295 } while (0);
318 #define SEC_IO_SIZE 0x10000
321 #define SEC_IER 0x1008
326 #define SEC_ISR 0x1010
327 #define SEC_ICR 0x1018
328 #define SEC_ID 0x1020
330 #define SEC_EUASR 0x1028
331 #define SEC_EUASR_RNGU(r) (((r) >> 0) & 0xF)
332 #define SEC_EUASR_PKEU(r) (((r) >> 8) & 0xF)
333 #define SEC_EUASR_KEU(r) (((r) >> 16) & 0xF)
334 #define SEC_EUASR_CRCU(r) (((r) >> 20) & 0xF)
335 #define SEC_EUASR_DEU(r) (((r) >> 32) & 0xF)
336 #define SEC_EUASR_AESU(r) (((r) >> 40) & 0xF)
337 #define SEC_EUASR_MDEU(r) (((r) >> 48) & 0xF)
338 #define SEC_EUASR_AFEU(r) (((r) >> 56) & 0xF)
340 #define SEC_MCR 0x1030
344 #define SEC_CHAN_CCR(n) (((n) * 0x100) + 0x1108)
354 #define SEC_CHAN_CSR(n) (((n) * 0x100) + 0x1110)
355 #define SEC_CHAN_CSR2_FFLVL_M 0x1FULL
357 #define SEC_CHAN_CSR2_GSTATE_M 0x0FULL
359 #define SEC_CHAN_CSR2_PSTATE_M 0x0FULL
361 #define SEC_CHAN_CSR2_MSTATE_M 0x3FULL
363 #define SEC_CHAN_CSR3_FFLVL_M 0x1FULL
365 #define SEC_CHAN_CSR3_MSTATE_M 0x1FFULL
367 #define SEC_CHAN_CSR3_PSTATE_M 0x7FULL
369 #define SEC_CHAN_CSR3_GSTATE_M 0x7FULL
372 #define SEC_CHAN_CDPR(n) (((n) * 0x100) + 0x1140)
373 #define SEC_CHAN_FF(n) (((n) * 0x100) + 0x1148)
376 #define SEC_EU_NONE 0x0
377 #define SEC_EU_AFEU 0x1
378 #define SEC_EU_DEU 0x2
379 #define SEC_EU_MDEU_A 0x3
380 #define SEC_EU_MDEU_B 0xB
381 #define SEC_EU_RNGU 0x4
382 #define SEC_EU_PKEU 0x5
383 #define SEC_EU_AESU 0x6
384 #define SEC_EU_KEU 0x7
385 #define SEC_EU_CRCU 0x8
388 #define SEC_DT_COMMON_NONSNOOP 0x02
389 #define SEC_DT_HMAC_SNOOP 0x04
392 #define SEC_AESU_MODE_ED (1ULL << 0)
396 #define SEC_DEU_MODE_ED (1ULL << 0)
402 #define SEC_MDEU_MODE_SHA1 0x00 /* MDEU A */
403 #define SEC_MDEU_MODE_SHA384 0x00 /* MDEU B */
404 #define SEC_MDEU_MODE_SHA256 0x01
405 #define SEC_MDEU_MODE_MD5 0x02 /* MDEU A */
406 #define SEC_MDEU_MODE_SHA512 0x02 /* MDEU B */
407 #define SEC_MDEU_MODE_SHA224 0x03