Lines Matching +full:0 +full:x170
36 #define XENON_SYS_OP_CTRL 0x0108
40 #define XENON_SYS_EXT_OP_CTRL 0x010C
43 #define XENON_SLOT_EMMC_CTRL 0x0130
48 #define XENON_CTRL2_MMC_HS200 0x5
49 #define XENON_CTRL2_MMC_HS400 0x6
52 #define XENON_EMMC_PHY_REG_BASE 0x170
59 #define XENON_WAIT_CYCLE_BEFORE_USING_MASK 0xF
61 #define XENON_FC_SYNC_EN_DURATION_MASK 0xF
63 #define XENON_FC_SYNC_RST_EN_DURATION_MASK 0xF
65 #define XENON_FC_SYNC_RST_DURATION_MASK 0xF
66 #define XENON_FC_SYNC_RST_DURATION_SHIFT 0
68 #define XENON_EMMC_PHY_FUNC_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x4)
72 #define XENON_DQ_DDR_MODE_MASK 0xFF
76 #define XENON_EMMC_PHY_PAD_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x8)
82 #define XENON_FC_ALL_CMOS_RECEIVER 0xF000
84 #define XENON_EMMC_PHY_PAD_CONTROL1 (XENON_EMMC_PHY_REG_BASE + 0xC)
89 #define XENON_EMMC_FC_DQ_PD 0xFF
90 #define XENON_EMMC_FC_DQ_PU (0xFF << 16)
92 #define XENON_EMMC_PHY_PAD_CONTROL2 (XENON_EMMC_PHY_REG_BASE + 0x10)
93 #define XENON_ZNR_MASK 0x1F
95 #define XENON_ZPR_MASK 0x1F
96 #define XENON_ZNR_DEF_VALUE 0xF
97 #define XENON_ZPR_DEF_VALUE 0xF
99 #define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18)
100 #define XENON_LOGIC_TIMING_VALUE 0x00AA8977