157 	uint16_t hostctrl2;  in sdhci_xenon_set_uhs_timing()  local
166 	hostctrl2 = sdhci_xenon_read_2(brdev, slot, SDHCI_HOST_CONTROL2);  in sdhci_xenon_set_uhs_timing()
167 	hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;  in sdhci_xenon_set_uhs_timing()
171 			hostctrl2 |= XENON_CTRL2_MMC_HS400;  in sdhci_xenon_set_uhs_timing()
173 			hostctrl2 |= XENON_CTRL2_MMC_HS200;  in sdhci_xenon_set_uhs_timing()
175 			hostctrl2 |= SDHCI_CTRL2_UHS_SDR104;  in sdhci_xenon_set_uhs_timing()
178 		hostctrl2 |= SDHCI_CTRL2_UHS_SDR50;  in sdhci_xenon_set_uhs_timing()
182 			hostctrl2 |= SDHCI_CTRL2_UHS_DDR50;  in sdhci_xenon_set_uhs_timing()
184 			hostctrl2 |= SDHCI_CTRL2_UHS_SDR25;  in sdhci_xenon_set_uhs_timing()
186 		hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;  in sdhci_xenon_set_uhs_timing()
187 	sdhci_xenon_write_2(brdev, slot, SDHCI_HOST_CONTROL2, hostctrl2);  in sdhci_xenon_set_uhs_timing()
381 	uint16_t hostctrl2;  in sdhci_xenon_switch_vccq()  local
396 	hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2);  in sdhci_xenon_switch_vccq()
399 		if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))  in sdhci_xenon_switch_vccq()
401 		hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE;  in sdhci_xenon_switch_vccq()
402 		bus_write_2(sc->mem_res, SDHCI_HOST_CONTROL2, hostctrl2);  in sdhci_xenon_switch_vccq()
424 		hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2);  in sdhci_xenon_switch_vccq()
425 		if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))  in sdhci_xenon_switch_vccq()
432 		if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)  in sdhci_xenon_switch_vccq()
434 		hostctrl2 |= SDHCI_CTRL2_S18_ENABLE;  in sdhci_xenon_switch_vccq()
435 		bus_write_2(sc->mem_res, SDHCI_HOST_CONTROL2, hostctrl2);  in sdhci_xenon_switch_vccq()
457 		hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2);  in sdhci_xenon_switch_vccq()
458 		if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)  in sdhci_xenon_switch_vccq()