59 #define	PCI_SDHCI_IFPIO			0x00
60 #define	PCI_SDHCI_IFDMA			0x01
61 #define	PCI_SDHCI_IFVENDOR		0x02
63 #define	PCI_SLOT_INFO			0x40	/* 8 bits */
70 #define	SDHC_PCI_MODE_KEY		0xf9
71 #define	SDHC_PCI_MODE			0x150
72 #define	SDHC_PCI_MODE_SD20		0x10
73 #define	SDHC_PCI_BASE_FREQ_KEY		0xfc
74 #define	SDHC_PCI_BASE_FREQ		0xe1
82 	{ 0x08221180,	0xffff,	"RICOH R5C822 SD",
84 	{ 0xe8221180,	0xffff,	"RICOH R5CE822 SD",
87 	{ 0xe8231180,	0xffff,	"RICOH R5CE823 SD",
89 	{ 0x8034104c,	0xffff, "TI XX21/XX11 SD",
91 	{ 0x803c104c,	0xffff, "TI XX12 SD",
94 	{ 0x05501524,	0xffff, "ENE CB712 SD",
96 	{ 0x05511524,	0xffff, "ENE CB712 SD 2",
98 	{ 0x07501524,	0xffff, "ENE CB714 SD",
101 	{ 0x07511524,	0xffff, "ENE CB714 SD 2",
104 	{ 0x410111ab,	0xffff, "Marvell CaFe SD",
106 	{ 0x2381197B,	0xffff,	"JMicron JMB38X SD",
109 	{ 0x16bc14e4,	0xffff,	"Broadcom BCM577xx SDXC/MMC Card Reader",
111 	{ 0x0f148086,	0xffff,	"Intel Bay Trail eMMC 4.5 Controller",
117 	{ 0x0f158086,	0xffff,	"Intel Bay Trail SDXC Controller",
120 	{ 0x0f508086,	0xffff,	"Intel Bay Trail eMMC 4.5 Controller",
126 	{ 0x19db8086,	0xffff,	"Intel Denverton eMMC 5.0 Controller",
132 	{ 0x22948086,	0xffff,	"Intel Braswell eMMC 4.5.1 Controller",
139 	{ 0x22968086,	0xffff,	"Intel Braswell SDXC Controller",
142 	{ 0x5aca8086,	0xffff,	"Intel Apollo Lake SDXC Controller",
146 	{ 0x5acc8086,	0xffff,	"Intel Apollo Lake eMMC 5.0 Controller",
153 	{ 0,		0xffff,	NULL,
154 	    0 }
171     0, "Enable MSI interrupts");
178 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,  in sdhci_pci_read_1()
189 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,  in sdhci_pci_write_1()
199 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,  in sdhci_pci_read_2()
210 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,  in sdhci_pci_write_2()
220 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,  in sdhci_pci_read_4()
231 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,  in sdhci_pci_write_4()
262 	 * Enable SD2.0 mode.  in sdhci_lower_frequency()
263 	 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822.  in sdhci_lower_frequency()
265 	pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);  in sdhci_lower_frequency()
268 	pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);  in sdhci_lower_frequency()
274 	pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);  in sdhci_lower_frequency()
277 	pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);  in sdhci_lower_frequency()
286 	pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);  in sdhci_restore_frequency()
288 	pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);  in sdhci_restore_frequency()
291 	pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);  in sdhci_restore_frequency()
293 	pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);  in sdhci_restore_frequency()
305 	model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;  in sdhci_pci_probe()
311 	for (i = 0; sdhci_devices[i].model != 0; i++) {  in sdhci_pci_probe()
313 		    (sdhci_devices[i].subvendor == 0xffff ||  in sdhci_pci_probe()
339 	model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;  in sdhci_pci_attach()
342 	for (i = 0; sdhci_devices[i].model != 0; i++) {  in sdhci_pci_attach()
344 		    (sdhci_devices[i].subvendor == 0xffff ||  in sdhci_pci_attach()
367 	rid = 0;  in sdhci_pci_attach()
368 	if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0)  in sdhci_pci_attach()
371 		RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));  in sdhci_pci_attach()
378 	for (i = 0; i < slots; i++) {  in sdhci_pci_attach()
393 		if (sdhci_init_slot(dev, slot, i) != 0)  in sdhci_pci_attach()
406 	for (i = 0; i < sc->num_slots; i++) {  in sdhci_pci_attach()
410 	return (0);  in sdhci_pci_attach()
424 	for (i = 0; i < sc->num_slots; i++) {  in sdhci_pci_detach()
431 	return (0);  in sdhci_pci_detach()
441 	return (0);  in sdhci_pci_shutdown()
453 	for (i = 0; i < sc->num_slots; i++)  in sdhci_pci_suspend()
455 	return (0);  in sdhci_pci_suspend()
464 	for (i = 0; i < sc->num_slots; i++)  in sdhci_pci_resume()
471 	return (0);  in sdhci_pci_resume()
480 	for (i = 0; i < sc->num_slots; i++)  in sdhci_pci_intr()