319 	uint32_t prescale, div, val32, div_ratio;  in fsl_sdhc_fdt_set_clock()  local
322 	val32 = RD4(sc, SDHCI_CLOCK_CONTROL);  in fsl_sdhc_fdt_set_clock()
325 		WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHCI_FSL_CLK_SDCLKEN);  in fsl_sdhc_fdt_set_clock()
368 	val32 &= ~(SDHCI_FSL_CLK_DIVIDER_MASK | SDHCI_FSL_CLK_PRESCALE_MASK);  in fsl_sdhc_fdt_set_clock()
369 	val32 |= div << SDHCI_FSL_CLK_DIVIDER_SHIFT;  in fsl_sdhc_fdt_set_clock()
370 	val32 |= prescale << SDHCI_FSL_CLK_PRESCALE_SHIFT;  in fsl_sdhc_fdt_set_clock()
371 	val32 |= SDHCI_FSL_CLK_IPGEN | SDHCI_FSL_CLK_SDCLKEN;  in fsl_sdhc_fdt_set_clock()
372 	WR4(sc, SDHCI_CLOCK_CONTROL, val32);  in fsl_sdhc_fdt_set_clock()
379 	uint32_t wrk32, val32;  in sdhci_fsl_fdt_read_1()  local
386 		val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET |  in sdhci_fsl_fdt_read_1()
389 			val32 |= SDHCI_CTRL_4BITBUS;  in sdhci_fsl_fdt_read_1()
391 			val32 |= SDHCI_CTRL_8BITBUS;  in sdhci_fsl_fdt_read_1()
392 		return (val32);  in sdhci_fsl_fdt_read_1()
406 	uint32_t val32;  in sdhci_fsl_fdt_read_2()  local
424 		val32 = RD4(sc, SDHCI_INT_STATUS);  in sdhci_fsl_fdt_read_2()
425 		val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);  in sdhci_fsl_fdt_read_2()
426 		return (!!val32);  in sdhci_fsl_fdt_read_2()
436 	uint32_t wrk32, val32;  in sdhci_fsl_fdt_read_4()  local
445 	val32 = RD4(sc, off);  in sdhci_fsl_fdt_read_4()
448 		wrk32 = val32;  in sdhci_fsl_fdt_read_4()
449 		val32 &= SDHCI_FSL_PRES_COMPAT_MASK;  in sdhci_fsl_fdt_read_4()
450 		val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK;  in sdhci_fsl_fdt_read_4()
451 		val32 |= (wrk32 << 1) & SDHCI_STATE_CMD;  in sdhci_fsl_fdt_read_4()
454 	return (val32);  in sdhci_fsl_fdt_read_4()
472 	uint32_t val32;  in sdhci_fsl_fdt_write_1()  local
478 		val32 = RD4(sc, SDHCI_FSL_PROT_CTRL);  in sdhci_fsl_fdt_write_1()
479 		val32 &= ~SDHCI_FSL_PROT_CTRL_WIDTH_MASK;  in sdhci_fsl_fdt_write_1()
480 		val32 |= (val & SDHCI_CTRL_LED);  in sdhci_fsl_fdt_write_1()
483 			val32 |= SDHCI_FSL_PROT_CTRL_WIDTH_8BIT;  in sdhci_fsl_fdt_write_1()
486 			val32 |= (val & SDHCI_CTRL_4BITBUS);  in sdhci_fsl_fdt_write_1()
488 		val32 &= ~SDHCI_FSL_PROT_CTRL_DMA_MASK;  in sdhci_fsl_fdt_write_1()
489 		val32 &= ~(SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD);  in sdhci_fsl_fdt_write_1()
490 		val32 |= (val & (SDHCI_CTRL_CARD_DET |  in sdhci_fsl_fdt_write_1()
492 		WR4(sc, SDHCI_FSL_PROT_CTRL, val32);  in sdhci_fsl_fdt_write_1()
497 		val32 = RD4(sc, off & ~3);  in sdhci_fsl_fdt_write_1()
498 		val32 &= ~(UINT8_MAX << (off & 3) * 8);  in sdhci_fsl_fdt_write_1()
499 		val32 |= (val << (off & 3) * 8);  in sdhci_fsl_fdt_write_1()
500 		WR4(sc, off & ~3, val32);  in sdhci_fsl_fdt_write_1()
510 	uint32_t val32;  in sdhci_fsl_fdt_write_2()  local
540 		val32 = RD4(sc, off & ~3);  in sdhci_fsl_fdt_write_2()
541 		val32 &= ~(UINT16_MAX << (off & 3) * 8);  in sdhci_fsl_fdt_write_2()
542 		val32 |= ((val & UINT16_MAX) << (off & 3) * 8);  in sdhci_fsl_fdt_write_2()
543 		WR4(sc, off & ~3, val32);  in sdhci_fsl_fdt_write_2()