Lines Matching +full:0 +full:x1f4
63 #define CV181X_SYSCTRL_SD_PWRSW_CTRL 0x1F4
64 #define SD_PWRSW_CTRL_RESET_MASK 0x9
65 #define CVI_CV181X_SDHCI_VENDOR_OFFSET 0x200
66 #define CVI_CV181X_SDHCI_EMMC_CTRL (CVI_CV181X_SDHCI_VENDOR_OFFSET + 0x0)
67 #define EMMC_CTRL_RESET_MASK 0x302
68 #define CVI_CV181X_SDHCI_PHY_TX_RX_DLY (CVI_CV181X_SDHCI_VENDOR_OFFSET + 0x40)
69 #define PHY_TX_RX_DLY_RESET_MASK 0x1000100
70 #define CVI_CV181X_SDHCI_PHY_CONFIG (CVI_CV181X_SDHCI_VENDOR_OFFSET + 0x4C)
71 #define PHY_CONFIG_RESET_MASK 0x1
77 { NULL, 0 }
86 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in sdhci_fdt_cvitek_probe()
106 res = sc->mem_res[0]; in sdhci_fdt_cvitek_attach()
109 if (error != 0) { in sdhci_fdt_cvitek_attach()
126 return (0); in sdhci_fdt_cvitek_attach()