Lines Matching +full:sdhci +full:- +full:caps
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 /* Generic driver to attach sdhci controllers on simplebus.
60 #include <dev/sdhci/sdhci.h>
112 #define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask))
116 { "marvell,armada-380-sdhci", SDHCI_FDT_ARMADA38X },
117 { "qcom,sdhci-msm-v4", SDHCI_FDT_QUALCOMM },
118 { "rockchip,rk3399-sdhci-5.1", SDHCI_FDT_RK3399 },
120 { "rockchip,rk3568-dwcmshc", SDHCI_FDT_RK3568 },
121 { "xlnx,zynqmp-8.9a", SDHCI_FDT_XLNX_ZMP },
128 u_int caps; /* If we override SDHCI_CAPABILITIES */ member
199 node = ofw_bus_get_node(sc->dev); in sdhci_export_clocks()
202 device_printf(sc->dev, "cannot parse 'reg' property\n"); in sdhci_export_clocks()
207 "#clock-cells", &ncells); in sdhci_export_clocks()
209 device_printf(sc->dev, "couldn't find parent clocks\n"); in sdhci_export_clocks()
213 nclocks = ofw_bus_string_list_to_array(node, "clock-output-names", in sdhci_export_clocks()
219 clkdom = clkdom_create(sc->dev); in sdhci_export_clocks()
227 def.parent_names[0] = clk_get_name(sc->clk_xin); in sdhci_export_clocks()
232 device_printf(sc->dev, "cannot create clknode\n"); in sdhci_export_clocks()
237 clksc->clkdev = device_get_parent(sc->dev); in sdhci_export_clocks()
243 device_printf(sc->dev, "cannot finalize clkdom initialization\n"); in sdhci_export_clocks()
258 error = clk_get_by_ofw_name(dev, 0, "clk_xin", &sc->clk_xin); in sdhci_init_clocks()
263 error = clk_enable(sc->clk_xin); in sdhci_init_clocks()
268 error = clk_get_by_ofw_name(dev, 0, "clk_ahb", &sc->clk_ahb); in sdhci_init_clocks()
273 error = clk_enable(sc->clk_ahb); in sdhci_init_clocks()
288 error = phy_get_by_ofw_name(sc->dev, 0, "phy_arasan", &sc->phy); in sdhci_init_phy()
292 device_printf(sc->dev, "Could not get phy\n"); in sdhci_init_phy()
295 error = phy_enable(sc->phy); in sdhci_init_phy()
297 device_printf(sc->dev, "Could not enable phy\n"); in sdhci_init_phy()
310 node = ofw_bus_get_node(sc->dev); in sdhci_get_syscon()
311 if (OF_hasprop(node, "arasan,soc-ctl-syscon") && in sdhci_get_syscon()
312 syscon_get_by_ofw_property(sc->dev, node, in sdhci_get_syscon()
313 "arasan,soc-ctl-syscon", &sc->syscon) != 0) { in sdhci_get_syscon()
314 device_printf(sc->dev, "cannot get syscon handle\n"); in sdhci_get_syscon()
329 error = clk_get_freq(sc->clk_xin, &freq); in sdhci_init_rk3399()
338 SYSCON_WRITE_4(sc->syscon, RK3399_GRF_EMMCCORE_CON11, (mask << 16) | val); in sdhci_init_rk3399()
344 SYSCON_WRITE_4(sc->syscon, RK3399_GRF_EMMCCORE_CON0, (mask << 16) | val); in sdhci_init_rk3399()
354 return (bus_read_1(sc->mem_res[slot->num], off)); in sdhci_fdt_read_1()
363 bus_write_1(sc->mem_res[slot->num], off, val); in sdhci_fdt_write_1()
371 return (bus_read_2(sc->mem_res[slot->num], off)); in sdhci_fdt_read_2()
380 bus_write_2(sc->mem_res[slot->num], off, val); in sdhci_fdt_write_2()
389 val32 = bus_read_4(sc->mem_res[slot->num], off); in sdhci_fdt_read_4()
390 if (off == SDHCI_CAPABILITIES && sc->no_18v) in sdhci_fdt_read_4()
402 bus_write_4(sc->mem_res[slot->num], off, val); in sdhci_fdt_write_4()
411 bus_read_multi_4(sc->mem_res[slot->num], off, data, count); in sdhci_fdt_read_multi_4()
420 bus_write_multi_4(sc->mem_res[slot->num], off, data, count); in sdhci_fdt_write_multi_4()
429 for (i = 0; i < sc->num_slots; i++) in sdhci_fdt_intr()
430 sdhci_generic_intr(&sc->slots[i]); in sdhci_fdt_intr()
438 if (sc->wp_disabled) in sdhci_fdt_get_ro()
440 return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted); in sdhci_fdt_get_ro()
450 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == in sdhci_fdt_set_clock()
456 clk_set_freq(sc->clk_core, clock, 0); in sdhci_fdt_set_clock()
459 bus_write_4(sc->mem_res[slot->num], in sdhci_fdt_set_clock()
461 bus_write_4(sc->mem_res[slot->num], in sdhci_fdt_set_clock()
463 bus_write_4(sc->mem_res[slot->num], in sdhci_fdt_set_clock()
465 bus_write_4(sc->mem_res[slot->num], in sdhci_fdt_set_clock()
470 bus_write_4(sc->mem_res[slot->num], in sdhci_fdt_set_clock()
473 bus_write_4(sc->mem_res[slot->num], in sdhci_fdt_set_clock()
475 bus_write_4(sc->mem_res[slot->num], in sdhci_fdt_set_clock()
479 val = bus_read_4(sc->mem_res[slot->num], in sdhci_fdt_set_clock()
486 bus_write_4(sc->mem_res[slot->num], RK3568_EMMC_ATCTRL, in sdhci_fdt_set_clock()
488 bus_write_4(sc->mem_res[slot->num], in sdhci_fdt_set_clock()
491 bus_write_4(sc->mem_res[slot->num], in sdhci_fdt_set_clock()
494 bus_write_4(sc->mem_res[slot->num], in sdhci_fdt_set_clock()
510 sc->quirks = 0; in sdhci_fdt_probe()
511 sc->num_slots = 1; in sdhci_fdt_probe()
512 sc->max_clk = 0; in sdhci_fdt_probe()
517 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { in sdhci_fdt_probe()
519 sc->quirks = SDHCI_QUIRK_BROKEN_AUTO_STOP; in sdhci_fdt_probe()
520 device_set_desc(dev, "ARMADA38X SDHCI controller"); in sdhci_fdt_probe()
523 sc->quirks = SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | in sdhci_fdt_probe()
525 sc->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K; in sdhci_fdt_probe()
526 device_set_desc(dev, "Qualcomm FDT SDHCI controller"); in sdhci_fdt_probe()
529 device_set_desc(dev, "Rockchip RK3399 fdt SDHCI controller"); in sdhci_fdt_probe()
532 sc->quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; in sdhci_fdt_probe()
533 device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller"); in sdhci_fdt_probe()
536 device_set_desc(dev, "Rockchip RK3568 fdt SDHCI controller"); in sdhci_fdt_probe()
539 device_set_desc(dev, "ZynqMP generic fdt SDHCI controller"); in sdhci_fdt_probe()
547 /* Allow dts to patch quirks, slots, and max-frequency. */ in sdhci_fdt_probe()
549 sc->quirks = cid; in sdhci_fdt_probe()
550 if ((OF_getencprop(node, "num-slots", &cid, sizeof(cid))) > 0) in sdhci_fdt_probe()
551 sc->num_slots = cid; in sdhci_fdt_probe()
552 if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0) in sdhci_fdt_probe()
553 sc->max_clk = cid; in sdhci_fdt_probe()
554 if (OF_hasprop(node, "no-1-8-v")) in sdhci_fdt_probe()
555 sc->no_18v = true; in sdhci_fdt_probe()
556 if (OF_hasprop(node, "wp-inverted")) in sdhci_fdt_probe()
557 sc->wp_inverted = true; in sdhci_fdt_probe()
558 if (OF_hasprop(node, "disable-wp")) in sdhci_fdt_probe()
559 sc->wp_disabled = true; in sdhci_fdt_probe()
571 sc->dev = dev; in sdhci_fdt_attach()
575 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, in sdhci_fdt_attach()
577 if (sc->irq_res == NULL) { in sdhci_fdt_attach()
582 compat = ofw_bus_search_compatible(dev, compat_data)->ocd_data; in sdhci_fdt_attach()
603 device_printf(dev, "Cannot init RK3399 SDHCI\n"); in sdhci_fdt_attach()
610 if (clk_get_by_ofw_name(dev, 0, "core", &sc->clk_core)) { in sdhci_fdt_attach()
614 clk_enable(sc->clk_core); in sdhci_fdt_attach()
621 slots = sc->num_slots; /* number of slots determined in probe(). */ in sdhci_fdt_attach()
622 sc->num_slots = 0; in sdhci_fdt_attach()
624 slot = &sc->slots[sc->num_slots]; in sdhci_fdt_attach()
628 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, in sdhci_fdt_attach()
630 if (sc->mem_res[i] == NULL) { in sdhci_fdt_attach()
636 slot->quirks = sc->quirks; in sdhci_fdt_attach()
637 slot->caps = sc->caps; in sdhci_fdt_attach()
638 slot->max_clk = sc->max_clk; in sdhci_fdt_attach()
639 slot->sdma_boundary = sc->sdma_boundary; in sdhci_fdt_attach()
644 sc->num_slots++; in sdhci_fdt_attach()
646 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); in sdhci_fdt_attach()
649 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, in sdhci_fdt_attach()
650 NULL, sdhci_fdt_intr, sc, &sc->intrhand); in sdhci_fdt_attach()
657 for (i = 0; i < sc->num_slots; i++) in sdhci_fdt_attach()
658 sdhci_start_slot(&sc->slots[i]); in sdhci_fdt_attach()
670 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); in sdhci_fdt_detach()
671 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), in sdhci_fdt_detach()
672 sc->irq_res); in sdhci_fdt_detach()
674 for (i = 0; i < sc->num_slots; i++) { in sdhci_fdt_detach()
675 sdhci_cleanup_slot(&sc->slots[i]); in sdhci_fdt_detach()
677 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); in sdhci_fdt_detach()
700 /* SDHCI registers accessors */