1 /*-
8  * 1. Redistributions of source code must retain the above copyright
60 	{ "80860F14",	1, "Intel Bay Trail/Braswell eMMC 4.5/4.5.1 Controller",
65 	{ "80860F14",	3, "Intel Bay Trail/Braswell SDXC Controller",
68 	{ "80860F16",	0, "Intel Bay Trail/Braswell SDXC Controller",
71 	{ "80865ACA",	0, "Intel Apollo Lake SDXC Controller",
114 	bus_barrier(sc->mem_res, 0, 0xFF,  in sdhci_acpi_read_1()
116 	return bus_read_1(sc->mem_res, off);  in sdhci_acpi_read_1()
125 	bus_barrier(sc->mem_res, 0, 0xFF,  in sdhci_acpi_write_1()
127 	bus_write_1(sc->mem_res, off, val);  in sdhci_acpi_write_1()
136 	bus_barrier(sc->mem_res, 0, 0xFF,  in sdhci_acpi_read_2()
138 	return bus_read_2(sc->mem_res, off);  in sdhci_acpi_read_2()
147 	bus_barrier(sc->mem_res, 0, 0xFF,  in sdhci_acpi_write_2()
149 	bus_write_2(sc->mem_res, off, val);  in sdhci_acpi_write_2()
158 	bus_barrier(sc->mem_res, 0, 0xFF,  in sdhci_acpi_read_4()
160 	return bus_read_4(sc->mem_res, off);  in sdhci_acpi_read_4()
169 	bus_barrier(sc->mem_res, 0, 0xFF,  in sdhci_acpi_write_4()
171 	bus_write_4(sc->mem_res, off, val);  in sdhci_acpi_write_4()
180 	bus_read_multi_stream_4(sc->mem_res, off, data, count);  in sdhci_acpi_read_multi_4()
189 	bus_write_multi_stream_4(sc->mem_res, off, data, count);  in sdhci_acpi_write_multi_4()
202 	bus = slot->bus;  in sdhci_acpi_set_uhs_timing()
208 	acpi_dev = sc->acpi_dev;  in sdhci_acpi_set_uhs_timing()
213 	 * an AMD-specific DLL reset additionally is needed.  in sdhci_acpi_set_uhs_timing()
215 	if (strcmp(acpi_dev->hid, "AMDI0040") == 0 && acpi_dev->uid == 0) {  in sdhci_acpi_set_uhs_timing()
216 		ios = &slot->host.ios;  in sdhci_acpi_set_uhs_timing()
217 		timing = ios->timing;  in sdhci_acpi_set_uhs_timing()
223 		if (ios->clock > SD_SDR50_MAX &&  in sdhci_acpi_set_uhs_timing()
277 	device_set_desc(dev, acpi_dev->desc);  in sdhci_acpi_probe()
294 	sc->acpi_dev = acpi_dev;  in sdhci_acpi_attach()
295 	quirks = acpi_dev->quirks;  in sdhci_acpi_attach()
299 	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,  in sdhci_acpi_attach()
301 	if (sc->irq_res == NULL) {  in sdhci_acpi_attach()
307 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,  in sdhci_acpi_attach()
309 	if (sc->mem_res == NULL) {  in sdhci_acpi_attach()
318 	 * these latter require the timeout clock to be hardcoded to 1 MHz.  in sdhci_acpi_attach()
320 	if (strcmp(acpi_dev->hid, "80860F14") == 0 && acpi_dev->uid == 1 &&  in sdhci_acpi_attach()
321 	    SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES) == 0x446cc8b2 &&  in sdhci_acpi_attach()
322 	    SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES2) == 0x00000807)  in sdhci_acpi_attach()
326 	sc->slot.quirks = quirks;  in sdhci_acpi_attach()
328 	err = sdhci_init_slot(dev, &sc->slot, 0);  in sdhci_acpi_attach()
336 	err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,  in sdhci_acpi_attach()
337 	    NULL, sdhci_acpi_intr, sc, &sc->intrhand);  in sdhci_acpi_attach()
345 	sdhci_start_slot(&sc->slot);  in sdhci_acpi_attach()
355 	if (sc->intrhand)  in sdhci_acpi_detach()
356 		bus_teardown_intr(dev, sc->irq_res, sc->intrhand);  in sdhci_acpi_detach()
357 	if (sc->irq_res)  in sdhci_acpi_detach()
359 		    rman_get_rid(sc->irq_res), sc->irq_res);  in sdhci_acpi_detach()
361 	if (sc->mem_res) {  in sdhci_acpi_detach()
362 		sdhci_cleanup_slot(&sc->slot);  in sdhci_acpi_detach()
364 		    rman_get_rid(sc->mem_res), sc->mem_res);  in sdhci_acpi_detach()
386 	sdhci_generic_suspend(&sc->slot);  in sdhci_acpi_suspend()
396 	sdhci_generic_resume(&sc->slot);  in sdhci_acpi_resume()
408 	sdhci_generic_intr(&sc->slot);  in sdhci_acpi_intr()