Lines Matching +full:use +full:- +full:broken +full:- +full:interrupts

1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
7  * Redistribution and use in source and binary forms, with or without
21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
50 /* Controller has an off-by-one issue with timeout value */
52 /* Controller has broken read timings */
56 /* Data timeout is invalid, should use SD clock */
62 /* Hardware shifts the 136-bit response, don't do it in software. */
64 /* Wait to see reset bit asserted before waiting for de-asserted  */
70 /* Card insert/remove interrupts don't work, polling required. */
72 /* All controller slots are non-removable. */
74 /* Issue custom Intel controller reset sequence after power-up. */
76 /* Data timeout is invalid, use 1 MHz clock instead. */
84 /* Controller support for UHS DDR50 mode is broken. */
86 /* Controller support for eMMC HS200 mode is broken. */
90 /* Controller support for SDHCI_CTRL2_PRESET_VALUE is broken. */
92 /* Controller does not support or the support for ACMD12 is broken. */
96 /* SDMA boundary in SDHCI_BLOCK_SIZE broken - use front-end supplied value. */
271 #define	 SDHCI_CTRL2_MMC_HS400	0x0005	/* non-standard */
311 #define	 SDHCI_CAN_MMC_HS400	0x80000000	/* non-standard */
380 	struct callout	retune_callout;	/* Re-tuning mode 1 callout */
388 	uint32_t	retune_ticks;	/* Re-tuning callout ticks [hz] */
393 	uint8_t		retune_count;	/* Controller re-tuning count [s] */
394 	uint8_t		retune_mode;	/* Controller re-tuning mode */
398 	uint8_t		retune_req;	/* Re-tuning request status */
399 #define	SDHCI_RETUNE_REQ_NEEDED	0x01	/* Re-tuning w/o circuit reset needed */
400 #define	SDHCI_RETUNE_REQ_RESET	0x02	/* Re-tuning w/ circuit reset needed */
408 #define	SDHCI_USE_DMA		4	/* Use DMA for this req. */
427 /* performs generic clean-up for platform transfers */