Lines Matching +full:irq +full:- +full:status +full:- +full:read +full:- +full:quirk
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
81 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
82 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
83 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
85 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
87 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
88 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
89 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
91 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
121 /* CAM-related */
148 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
149 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
151 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
152 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
153 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
154 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
204 retval += printf("%s-slot%d: %s", in slot_printf()
205 device_get_nameunit(slot->bus), slot->num, buf); in slot_printf()
216 retval = sbuf_printf(s, "%s-slot%d: ", device_get_nameunit(slot->bus), slot->num); in slot_sprintf()
240 slot_sprintf(slot, s, "Wake-up: 0x%08x | Clock: 0x%08x\n", in sdhci_dumpregs_buf()
292 int host_caps = slot->host.caps; in sdhci_dumpcaps_buf()
293 int caps = slot->caps; in sdhci_dumpcaps_buf()
297 slot->max_clk / 1000000, in sdhci_dumpcaps_buf()
304 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "", in sdhci_dumpcaps_buf()
310 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO", in sdhci_dumpcaps_buf()
311 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" : in sdhci_dumpcaps_buf()
312 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" : in sdhci_dumpcaps_buf()
326 slot_sprintf(slot, s, "UHS-I:%s%s%s%s%s\n", in sdhci_dumpcaps_buf()
332 if (slot->opt & SDHCI_TUNING_SUPPORTED) in sdhci_dumpcaps_buf()
334 "Re-tuning count %d secs, mode %d\n", in sdhci_dumpcaps_buf()
335 slot->retune_count, slot->retune_mode + 1); in sdhci_dumpcaps_buf()
375 if (slot->opt & SDHCI_TUNING_ENABLED) { in sdhci_tuning_intmask()
377 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 || in sdhci_tuning_intmask()
378 slot->retune_mode == SDHCI_RETUNE_MODE_3) in sdhci_tuning_intmask()
388 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL); in sdhci_init()
391 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | in sdhci_init()
398 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && in sdhci_init()
399 !(slot->opt & SDHCI_NON_REMOVABLE)) { in sdhci_init()
400 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; in sdhci_init()
403 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); in sdhci_init()
404 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); in sdhci_init()
417 if (clock == slot->clock) in sdhci_set_clock()
419 clock = SDHCI_SET_CLOCK(slot->bus, slot, clock); in sdhci_set_clock()
420 slot->clock = clock; in sdhci_set_clock()
425 /* If no clock requested - leave it so. */ in sdhci_set_clock()
430 clk_base = slot->max_clk; in sdhci_set_clock()
431 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { in sdhci_set_clock()
451 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) in sdhci_set_clock()
452 slot->timeout_clk = slot->clock / 1000; in sdhci_set_clock()
454 if (slot->version < SDHCI_SPEC_300) { in sdhci_set_clock()
500 timeout--; in sdhci_set_clock()
514 if (slot->power == power) in sdhci_set_power()
517 slot->power = power; in sdhci_set_power()
522 /* If power down requested - leave it so. */ in sdhci_set_power()
555 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { in sdhci_set_power()
570 buffer = slot->curcmd->data->data; in sdhci_read_block_pio()
571 buffer += slot->offset; in sdhci_read_block_pio()
574 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE) in sdhci_read_block_pio()
575 left = min(slot->curcmd->data->block_size, in sdhci_read_block_pio()
576 slot->curcmd->data->len - slot->offset); in sdhci_read_block_pio()
579 left = min(512, slot->curcmd->data->len - slot->offset); in sdhci_read_block_pio()
580 slot->offset += left; in sdhci_read_block_pio()
583 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) in sdhci_read_block_pio()
594 left -= 4; in sdhci_read_block_pio()
607 left--; in sdhci_read_block_pio()
619 buffer = slot->curcmd->data->data; in sdhci_write_block_pio()
620 buffer += slot->offset; in sdhci_write_block_pio()
623 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE) { in sdhci_write_block_pio()
624 left = min(slot->curcmd->data->block_size, in sdhci_write_block_pio()
625 slot->curcmd->data->len - slot->offset); in sdhci_write_block_pio()
628 left = min(512, slot->curcmd->data->len - slot->offset); in sdhci_write_block_pio()
629 slot->offset += left; in sdhci_write_block_pio()
638 left -= 4; in sdhci_write_block_pio()
652 left--; in sdhci_write_block_pio()
662 /* Read as many blocks as possible. */ in sdhci_transfer_pio()
663 if (slot->curcmd->data->flags & MMC_DATA_READ) { in sdhci_transfer_pio()
667 if (slot->offset >= slot->curcmd->data->len) in sdhci_transfer_pio()
674 if (slot->offset >= slot->curcmd->data->len) in sdhci_transfer_pio()
689 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
691 if (slot->card_present == 0) {
693 if (slot->dev == NULL) {
695 /* If card is present - attach mmc bus. */
699 slot->card_present = 1;
700 mmccam_start_discovery(slot->sim);
703 d = slot->dev = device_add_child(slot->bus, "mmc", DEVICE_UNIT_ANY);
714 if (slot->card_present == 1) {
716 if (slot->dev != NULL) {
717 d = slot->dev;
719 /* If no card present - detach mmc bus. */
722 slot->dev = NULL;
724 slot->card_present = 0;
725 mmccam_start_discovery(slot->sim);
728 slot->intmask &= ~sdhci_tuning_intmask(slot);
729 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
730 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
731 slot->opt &= ~SDHCI_TUNING_ENABLED;
733 callout_drain(&slot->retune_callout);
734 device_delete_child(slot->bus, d);
753 * the task to delete the child device. No debouncing -- gone is gone,
754 * because once power is removed, a full card re-init is needed, and
758 was_present = slot->card_present;
760 was_present = slot->dev != NULL;
764 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS);
766 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
785 SDHCI_GET_CARD_PRESENT(slot->bus, slot));
786 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS,
795 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY)) {
797 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K;
799 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_8K;
801 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_16K;
803 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_32K;
805 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_64K;
807 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_128K;
809 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_256K;
811 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_512K;
813 slot->sdma_bbufsz = SDHCI_SDMA_BNDRY_TO_BBUFSZ(slot->sdma_boundary);
823 err = bus_dma_tag_create(bus_get_dma_tag(slot->bus), slot->sdma_bbufsz,
825 slot->sdma_bbufsz, 1, slot->sdma_bbufsz, BUS_DMA_ALLOCNOW,
826 NULL, NULL, &slot->dmatag);
832 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
833 BUS_DMA_NOWAIT, &slot->dmamap);
836 bus_dma_tag_destroy(slot->dmatag);
840 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
841 (void *)slot->dmamem, slot->sdma_bbufsz, sdhci_getaddr,
842 &slot->paddr, 0);
843 if (err != 0 || slot->paddr == 0) {
845 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
846 bus_dma_tag_destroy(slot->dmatag);
860 bus_dmamap_unload(slot->dmatag, slot->dmamap);
861 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
862 bus_dma_tag_destroy(slot->dmatag);
877 slot->num = num;
878 slot->bus = dev;
880 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
882 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) {
883 caps = slot->caps;
884 caps2 = slot->caps2;
887 if (slot->version >= SDHCI_SPEC_300)
892 if (slot->version >= SDHCI_SPEC_300) {
901 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE;
905 if (slot->version >= SDHCI_SPEC_300)
912 slot->max_clk = freq * 1000000;
918 if (slot->max_clk == 0) {
919 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
925 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
926 slot->timeout_clk = slot->max_clk / 1000;
927 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
928 slot->timeout_clk = 1000;
930 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >>
933 slot->timeout_clk *= 1000;
940 if (slot->timeout_clk == 0) {
942 "frequency, setting BROKEN_TIMEOUT quirk.\n");
943 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
946 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
947 slot->host.f_max = slot->max_clk;
948 slot->host.host_ocr = 0;
950 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
952 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
956 * sometimes support 1.8v for non-removable devices.
958 if ((caps & SDHCI_CAN_VDD_180) && (slot->version < SDHCI_SPEC_300 ||
959 (slot->opt & SDHCI_SLOT_EMBEDDED)))
960 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
961 if (slot->host.host_ocr == 0) {
966 host_caps = slot->host.caps;
972 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC)
974 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY)
977 /* Determine supported UHS-I and eMMC modes. */
982 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200))
987 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50))
989 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52)
991 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 &&
994 if (slot->quirks & SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 &&
999 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the
1003 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1005 if (kobj_method == &kobj_desc->deflt)
1016 * Disable UHS-I and eMMC modes that require (re-)tuning if either
1017 * the tune or re-tune method is the default NULL implementation.
1020 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1022 if (kobj_method == &kobj_desc->deflt)
1025 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1027 if (kobj_method == &kobj_desc->deflt) {
1034 slot->opt |= SDHCI_TUNING_SUPPORTED;
1035 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF,
1037 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF,
1039 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF,
1042 slot->opt |= SDHCI_SDR50_NEEDS_TUNING;
1043 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >>
1045 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) {
1046 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >>
1048 if (slot->retune_count > 0xb) {
1049 slot_printf(slot, "Unknown re-tuning count "
1050 "%x, using 1 sec\n", slot->retune_count);
1051 slot->retune_count = 1;
1052 } else if (slot->retune_count != 0)
1053 slot->retune_count =
1054 1 << (slot->retune_count - 1);
1074 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1076 if (kobj_method == &kobj_desc->deflt)
1078 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq)
1088 slot->host.caps = host_caps;
1092 slot->opt |= SDHCI_HAVE_DMA;
1094 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
1095 slot->opt &= ~SDHCI_HAVE_DMA;
1096 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
1097 slot->opt |= SDHCI_HAVE_DMA;
1098 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
1099 slot->opt |= SDHCI_NON_REMOVABLE;
1102 * Use platform-provided transfer backend
1105 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
1106 slot->opt &= ~SDHCI_HAVE_DMA;
1108 if (slot->opt & SDHCI_HAVE_DMA) {
1111 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1112 free(slot->tune_req, M_DEVBUF);
1113 free(slot->tune_cmd, M_DEVBUF);
1114 free(slot->tune_data, M_DEVBUF);
1126 slot->timeout = 10;
1127 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
1128 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
1129 "timeout", CTLFLAG_RWTUN, &slot->timeout, 0,
1131 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
1132 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0,
1134 callout_init(&slot->card_poll_callout, 1);
1135 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
1136 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0);
1138 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
1139 !(slot->opt & SDHCI_NON_REMOVABLE)) {
1140 callout_reset(&slot->card_poll_callout,
1146 snprintf(node_name, sizeof(node_name), "slot%d", slot->num);
1153 OID_AUTO, "quirks", CTLFLAG_RD, &slot->quirks, 0, "Slot quirks");
1186 callout_drain(&slot->timeout_callout);
1187 callout_drain(&slot->card_poll_callout);
1188 callout_drain(&slot->retune_callout);
1189 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
1190 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task);
1193 d = slot->dev;
1194 slot->dev = NULL;
1197 device_delete_child(slot->bus, d);
1200 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL);
1202 if (slot->opt & SDHCI_HAVE_DMA)
1204 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1205 free(slot->tune_req, M_DEVBUF);
1206 free(slot->tune_cmd, M_DEVBUF);
1207 free(slot->tune_data, M_DEVBUF);
1221 * Otherwise, we'd need to indicate re-tuning including circuit reset
1222 * being required at least for re-tuning modes 1 and 2 ourselves.
1224 callout_drain(&slot->retune_callout);
1226 slot->opt &= ~SDHCI_TUNING_ENABLED;
1227 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL);
1251 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
1252 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
1258 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
1260 clock = slot->clock;
1261 slot->clock = 0;
1266 slot->clock = 0;
1267 slot->power = 0;
1272 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
1276 * so a fast read after write returns 0 even if reset process is
1285 timeout--;
1300 timeout--;
1309 if (slot->version >= SDHCI_SPEC_300)
1310 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
1312 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
1319 if (slot->opt & SDHCI_NON_REMOVABLE)
1331 if (slot->version < SDHCI_SPEC_300)
1335 ios = &slot->host.ios;
1339 if (ios->clock > SD_SDR50_MAX) {
1340 if (ios->timing == bus_timing_mmc_hs400 ||
1341 ios->timing == bus_timing_mmc_hs400es)
1346 else if (ios->clock > SD_SDR25_MAX)
1348 else if (ios->clock > SD_SDR12_MAX) {
1349 if (ios->timing == bus_timing_uhs_ddr50 ||
1350 ios->timing == bus_timing_mmc_ddr52)
1354 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
1357 sdhci_set_clock(slot, ios->clock);
1364 struct mmc_ios *ios = &slot->host.ios;
1368 if (ios->power_mode == power_off) {
1373 sdhci_set_clock(slot, ios->clock);
1374 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
1375 if (ios->bus_width == bus_width_8) {
1376 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
1377 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1378 } else if (ios->bus_width == bus_width_4) {
1379 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1380 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
1381 } else if (ios->bus_width == bus_width_1) {
1382 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1383 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1385 panic("Invalid bus width: %d", ios->bus_width);
1387 if (ios->clock > SD_SDR12_MAX &&
1388 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
1389 slot->hostctrl |= SDHCI_CTRL_HISPD;
1391 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
1392 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1395 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
1396 SDHCI_RESET(slot->bus, slot,
1411 if (slot->version < SDHCI_SPEC_300)
1415 vccq = slot->host.ios.vccq;
1432 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
1453 sdhci_set_clock(slot, slot->host.ios.clock);
1462 const struct mmc_ios *ios = &slot->host.ios;
1468 if (!(slot->opt & SDHCI_TUNING_SUPPORTED))
1471 slot->retune_ticks = slot->retune_count * hz;
1474 switch (ios->timing) {
1482 * latch data from the devices so periodic re-tuning isn't
1486 slot->retune_ticks = 0;
1493 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING)
1503 tune_cmd = slot->tune_cmd;
1505 tune_cmd->opcode = opcode;
1506 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1507 tune_data = tune_cmd->data = slot->tune_data;
1509 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
1510 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 :
1512 tune_data->flags = MMC_DATA_READ;
1513 tune_data->mrq = tune_cmd->mrq = slot->tune_req;
1515 slot->opt &= ~SDHCI_TUNING_ENABLED;
1518 slot->opt |= SDHCI_TUNING_ENABLED;
1519 slot->intmask |= sdhci_tuning_intmask(slot);
1520 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
1521 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1522 if (slot->retune_ticks) {
1523 callout_reset(&slot->retune_callout, slot->retune_ticks,
1537 if (!(slot->opt & SDHCI_TUNING_ENABLED))
1541 if (slot->host.ios.timing == bus_timing_mmc_hs400)
1550 * EIO re-tuning failed (but it did work initially).
1552 * In both cases, we should retry at later point if periodic re-tuning
1553 * is enabled. Note that due to slot->retune_req not being cleared in
1555 * re-tuning with the next request anyway, though.
1557 if (slot->retune_ticks) {
1558 callout_reset(&slot->retune_callout, slot->retune_ticks,
1576 if (slot->req != NULL)
1580 opt = slot->opt;
1581 slot->opt = opt & ~SDHCI_HAVE_DMA;
1587 intmask = slot->intmask;
1588 slot->intmask = SDHCI_INT_DATA_AVAIL;
1599 tune_req = slot->tune_req;
1600 tune_cmd = slot->tune_cmd;
1603 tune_req->cmd = tune_cmd;
1604 tune_req->done = sdhci_req_wakeup;
1605 tune_req->done_data = slot;
1606 slot->req = tune_req;
1607 slot->flags = 0;
1609 while (!(tune_req->flags & MMC_REQ_DONE))
1610 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0);
1611 if (!(tune_req->flags & MMC_TUNE_DONE))
1616 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK)
1623 * SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE in slot->intmask
1627 slot->opt = opt;
1628 slot->intmask = intmask;
1635 slot->retune_req = 0;
1642 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1651 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
1662 if (slot->ccb != NULL && slot->curcmd != NULL) {
1663 callout_stop(&slot->timeout_callout);
1664 ccb = slot->ccb;
1665 slot->ccb = NULL;
1666 slot->curcmd = NULL;
1670 mmcio = &ccb->mmcio;
1672 ccb->ccb_h.status =
1673 (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR);
1683 if (slot->req != NULL && slot->curcmd != NULL) {
1684 callout_stop(&slot->timeout_callout);
1685 req = slot->req;
1686 slot->req = NULL;
1687 slot->curcmd = NULL;
1688 req->done(req);
1697 req->flags |= MMC_REQ_DONE;
1706 if (slot->curcmd != NULL) {
1709 SDHCI_RESET(slot->bus, slot,
1711 slot->curcmd->error = MMC_ERR_TIMEOUT;
1714 slot_printf(slot, "Spurious timeout - no active command\n");
1727 if (data->len > 512 || data->block_count > 1) {
1729 if (data->block_count == 0 && __predict_true(
1731 slot->ccb->mmcio.stop.opcode == MMC_STOP_TRANSMISSION &&
1733 slot->req->stop != NULL &&
1735 !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)))
1738 if (data->flags & MMC_DATA_READ)
1740 if (slot->flags & SDHCI_USE_DMA)
1752 slot->curcmd = cmd;
1753 slot->cmd_done = 0;
1755 cmd->error = MMC_ERR_NONE;
1758 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1760 cmd->error = MMC_ERR_FAILED;
1769 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
1770 slot->power == 0 ||
1771 slot->clock == 0) {
1774 slot->power, slot->clock);
1775 cmd->error = MMC_ERR_FAILED;
1782 if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY))
1787 * be set below but no actual data is ever read from the controller.
1790 if (cmd == &slot->ccb->mmcio.stop ||
1792 if (cmd == slot->req->stop ||
1794 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1795 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))
1802 * busy indications. In those cases, this wait-loop serves the purpose
1805 * (It's usually more like 20-30ms in the real world.)
1813 cmd->error = MMC_ERR_FAILED;
1817 timeout--;
1822 if (!(cmd->flags & MMC_RSP_PRESENT))
1824 else if (cmd->flags & MMC_RSP_136)
1826 else if (cmd->flags & MMC_RSP_BUSY)
1830 if (cmd->flags & MMC_RSP_CRC)
1832 if (cmd->flags & MMC_RSP_OPCODE)
1834 if (cmd->data != NULL)
1836 if (cmd->opcode == MMC_STOP_TRANSMISSION)
1839 sdhci_start_data(slot, cmd->data);
1845 if (slot->data_done == 0) {
1847 slot->intmask &= ~SDHCI_INT_RESPONSE);
1850 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
1852 sdhci_set_transfer_mode(slot, cmd->data);
1855 cmd->opcode, flags);
1858 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
1860 callout_reset(&slot->timeout_callout, slot->timeout * hz,
1873 __func__, slot->curcmd->error, slot->curcmd->flags);
1874 slot->cmd_done = 1;
1880 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK &&
1881 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1882 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |=
1884 /* In case of error - reset host and return. */
1885 if (slot->curcmd->error) {
1886 if (slot->curcmd->error == MMC_ERR_BADCRC)
1887 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1888 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
1889 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
1893 /* If command has response - fetch it. */
1894 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1895 if (slot->curcmd->flags & MMC_RSP_136) {
1900 if (slot->quirks &
1902 slot->curcmd->resp[3 - i] = val;
1904 slot->curcmd->resp[3 - i] =
1910 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1914 slot->curcmd->resp[0], slot->curcmd->resp[1],
1915 slot->curcmd->resp[2], slot->curcmd->resp[3]);
1917 /* If data ready - finish. */
1918 if (slot->data_done)
1928 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1929 slot->data_done = 1;
1933 slot->data_done = 0;
1937 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
1942 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1947 /* Compensate for an off-by-one error in the CaFe chip.*/
1949 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
1959 if ((slot->opt & SDHCI_HAVE_DMA))
1960 slot->flags |= SDHCI_USE_DMA;
1962 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1963 (data->len <= 512))
1964 slot->flags &= ~SDHCI_USE_DMA;
1966 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1967 ((data->len) & 0x3))
1968 slot->flags &= ~SDHCI_USE_DMA;
1970 if (slot->flags & SDHCI_USE_DMA) {
1971 sdma_bbufsz = slot->sdma_bbufsz;
1972 if (data->flags & MMC_DATA_READ)
1973 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1976 memcpy(slot->dmamem, data->data, ulmin(data->len,
1978 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1981 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1986 if (data->len == sdma_bbufsz)
1987 slot->intmask &= ~SDHCI_INT_DMA_END;
1989 slot->intmask |= SDHCI_INT_DMA_END;
1990 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1993 slot->offset = 0;
1995 if (data->flags & MMC_DATA_BLOCK_SIZE) {
1997 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, data->block_size);
1998 blkcnt = data->block_count;
2006 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, ulmin(data->len, 512));
2007 blkcnt = howmany(data->len, 512);
2020 struct mmc_data *data = slot->curcmd->data;
2026 if (!slot->cmd_done) {
2028 slot->intmask |= SDHCI_INT_RESPONSE);
2031 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) &&
2032 slot->curcmd->data != NULL) {
2033 if (data->flags & MMC_DATA_READ) {
2034 left = data->len - slot->offset;
2035 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2037 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
2038 ulmin(left, slot->sdma_bbufsz));
2040 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2043 slot->data_done = 1;
2044 /* If there was error - reset the host. */
2045 if (slot->curcmd->error) {
2046 if (slot->curcmd->error == MMC_ERR_BADCRC)
2047 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2048 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2049 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
2053 /* If we already have command response - finish. */
2054 if (slot->cmd_done)
2065 ccb = slot->ccb;
2069 mmcio = &ccb->mmcio;
2070 if (!(slot->flags & CMD_STARTED)) {
2071 slot->flags |= CMD_STARTED;
2072 sdhci_start_command(slot, &mmcio->cmd);
2079 * and IRQ storms on BBB, Wandboard behaves fine.
2081 if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) {
2082 slot->flags |= STOP_STARTED;
2083 sdhci_start_command(slot, &mmcio->stop);
2088 slot_printf(slot, "result: %d\n", mmcio->cmd.error);
2089 if (mmcio->cmd.error == 0 &&
2090 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
2091 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2092 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
2103 req = slot->req;
2107 if (!(slot->flags & CMD_STARTED)) {
2108 slot->flags |= CMD_STARTED;
2109 sdhci_start_command(slot, req->cmd);
2112 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) &&
2113 !(slot->flags & STOP_STARTED) && req->stop) {
2114 slot->flags |= STOP_STARTED;
2115 sdhci_start_command(slot, req->stop);
2119 slot_printf(slot, "result: %d\n", req->cmd->error);
2120 if (!req->cmd->error &&
2121 ((slot->curcmd == req->stop &&
2122 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) ||
2123 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2124 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2125 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
2139 if (slot->req != NULL) {
2146 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
2147 (req->cmd->data)?(u_int)req->cmd->data->len:0,
2148 (req->cmd->data)?req->cmd->data->flags:0);
2150 slot->req = req;
2151 slot->flags = 0;
2155 while (slot->req != NULL) {
2182 while (slot->bus_busy)
2183 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
2184 slot->bus_busy++;
2186 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
2198 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
2199 slot->bus_busy--;
2209 if (!slot->curcmd) {
2216 slot->curcmd->error = MMC_ERR_TIMEOUT;
2218 slot->curcmd->error = MMC_ERR_BADCRC;
2220 slot->curcmd->error = MMC_ERR_FIFO;
2232 if (!slot->curcmd) {
2238 if (slot->curcmd->data == NULL &&
2239 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
2247 slot->curcmd->error = MMC_ERR_TIMEOUT;
2249 slot->curcmd->error = MMC_ERR_BADCRC;
2250 if (slot->curcmd->data == NULL &&
2254 "there is busy-only command.\n", intmask);
2256 slot->curcmd->error = MMC_ERR_INVALID;
2258 if (slot->curcmd->error) {
2265 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK ||
2266 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) {
2267 slot->req->flags |= MMC_TUNE_DONE;
2274 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
2275 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
2276 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot,
2278 slot->flags |= PLATFORM_DATA_STARTED;
2284 data = slot->curcmd->data;
2285 sdma_bbufsz = slot->sdma_bbufsz;
2288 left = data->len - slot->offset;
2289 if (data->flags & MMC_DATA_READ) {
2290 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2292 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
2295 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2299 slot->offset += sdma_bbufsz;
2300 left = data->len - slot->offset;
2301 if (data->flags & MMC_DATA_READ) {
2302 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2305 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
2307 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2315 slot->intmask &= ~SDHCI_INT_DMA_END;
2316 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2319 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
2323 if (slot->flags & PLATFORM_DATA_STARTED) {
2324 slot->flags &= ~PLATFORM_DATA_STARTED;
2325 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2330 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
2331 if (slot->flags & PLATFORM_DATA_STARTED) {
2332 slot->flags &= ~PLATFORM_DATA_STARTED;
2333 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2343 if (!slot->curcmd) {
2350 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2360 /* Read slot interrupt status. */
2373 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2374 if (slot->curcmd) {
2375 slot->curcmd->error = MMC_ERR_BADCRC;
2379 /* Handle re-tuning interrupt. */
2381 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
2385 slot->intmask &=
2387 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE :
2389 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
2390 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2443 *result = slot->host.ios.bus_mode;
2446 *result = slot->host.ios.bus_width;
2449 *result = slot->host.ios.chip_select;
2452 *result = slot->host.ios.clock;
2455 *result = slot->host.f_min;
2458 *result = slot->host.f_max;
2461 *result = slot->host.host_ocr;
2464 *result = slot->host.mode;
2467 *result = slot->host.ocr;
2470 *result = slot->host.ios.power_mode;
2473 *result = slot->host.ios.vdd;
2476 if (slot->opt & SDHCI_TUNING_ENABLED) {
2477 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) {
2481 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) {
2489 *result = slot->host.ios.vccq;
2492 *result = slot->host.caps;
2495 *result = slot->host.ios.timing;
2499 * Re-tuning modes 1 and 2 restrict the maximum data length
2500 * per read/write command to 4 MiB.
2502 if (slot->opt & SDHCI_TUNING_ENABLED &&
2503 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2504 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2534 slot->host.ios.bus_mode = value;
2537 slot->host.ios.bus_width = value;
2540 slot->host.ios.chip_select = value;
2544 max_clock = slot->max_clk;
2547 if (slot->version < SDHCI_SPEC_300) {
2563 slot->host.ios.clock = clock;
2565 slot->host.ios.clock = 0;
2568 slot->host.mode = value;
2571 slot->host.ocr = value;
2574 slot->host.ios.power_mode = value;
2577 slot->host.ios.vdd = value;
2580 slot->host.ios.vccq = value;
2583 slot->host.ios.timing = value;
2601 if ((slot->devq = cam_simq_alloc(1)) == NULL)
2604 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF);
2605 slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll,
2606 "sdhci_slot", slot, device_get_unit(slot->bus),
2607 &slot->sim_mtx, 1, 1, slot->devq);
2609 if (slot->sim == NULL) {
2610 cam_simq_free(slot->devq);
2615 mtx_lock(&slot->sim_mtx);
2616 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) {
2617 slot_printf(slot, "cannot register SCSI pass-through bus\n");
2618 cam_sim_free(slot->sim, FALSE);
2619 cam_simq_free(slot->devq);
2620 mtx_unlock(&slot->sim_mtx);
2623 mtx_unlock(&slot->sim_mtx);
2625 /* End CAM-specific init */
2626 slot->card_present = 0;
2631 if (slot->sim != NULL) {
2632 mtx_lock(&slot->sim_mtx);
2633 xpt_bus_deregister(cam_sim_path(slot->sim));
2634 cam_sim_free(slot->sim, FALSE);
2635 mtx_unlock(&slot->sim_mtx);
2638 if (slot->devq != NULL)
2639 cam_simq_free(slot->devq);
2649 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2654 mtx_assert(&slot->sim_mtx, MA_OWNED);
2656 switch (ccb->ccb_h.func_code) {
2658 mmc_path_inq(&ccb->cpi, "Deglitch Networks", sim, maxphys);
2664 struct ccb_trans_settings *cts = &ccb->cts;
2670 cts->protocol = PROTO_MMCSD;
2671 cts->protocol_version = 1;
2672 cts->transport = XPORT_MMCSD;
2673 cts->transport_version = 1;
2674 cts->xport_specific.valid = 0;
2675 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr;
2676 cts->proto_specific.mmc.host_f_min = slot->host.f_min;
2677 cts->proto_specific.mmc.host_f_max = slot->host.f_max;
2678 cts->proto_specific.mmc.host_caps = slot->host.caps;
2680 * Re-tuning modes 1 and 2 restrict the maximum data length
2681 * per read/write command to 4 MiB.
2683 if (slot->opt & SDHCI_TUNING_ENABLED &&
2684 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2685 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2690 cts->proto_specific.mmc.host_max_data = max_data;
2692 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios));
2693 ccb->ccb_h.status = CAM_REQ_CMP;
2701 ccb->ccb_h.status = CAM_REQ_CMP;
2706 ccb->ccb_h.status = CAM_REQ_CMP;
2710 * Here is the HW-dependent part of
2717 ccb->ccb_h.status = CAM_REQ_INPROG;
2722 ccb->ccb_h.status = CAM_REQ_INVALID;
2743 max_clock = slot->max_clk;
2746 if (slot->version < SDHCI_SPEC_300) {
2769 ios = &slot->host.ios;
2770 cts = &ccb->cts.proto_specific.mmc;
2771 new_ios = &cts->ios;
2774 if (cts->ios_valid & MMC_CLK) {
2775 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock);
2777 slot_printf(slot, "Clock => %d\n", ios->clock);
2779 if (cts->ios_valid & MMC_VDD) {
2780 ios->vdd = new_ios->vdd;
2782 slot_printf(slot, "VDD => %d\n", ios->vdd);
2784 if (cts->ios_valid & MMC_CS) {
2785 ios->chip_select = new_ios->chip_select;
2787 slot_printf(slot, "CS => %d\n", ios->chip_select);
2789 if (cts->ios_valid & MMC_BW) {
2790 ios->bus_width = new_ios->bus_width;
2792 slot_printf(slot, "Bus width => %d\n", ios->bus_width);
2794 if (cts->ios_valid & MMC_PM) {
2795 ios->power_mode = new_ios->power_mode;
2797 slot_printf(slot, "Power mode => %d\n", ios->power_mode);
2799 if (cts->ios_valid & MMC_BT) {
2800 ios->timing = new_ios->timing;
2802 slot_printf(slot, "Timing => %d\n", ios->timing);
2804 if (cts->ios_valid & MMC_BM) {
2805 ios->bus_mode = new_ios->bus_mode;
2807 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode);
2809 if (cts->ios_valid & MMC_VCCQ) {
2810 ios->vccq = new_ios->vccq;
2812 slot_printf(slot, "VCCQ => %d\n", ios->vccq);
2815 /* XXX Provide a way to call a chip-specific IOS update, required for TI */
2822 struct mmc_ios *ios = &slot->host.ios;
2826 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing);
2829 if (ios->power_mode == power_off) {
2834 sdhci_set_clock(slot, ios->clock);
2835 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
2836 if (ios->bus_width == bus_width_8) {
2837 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
2838 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
2839 } else if (ios->bus_width == bus_width_4) {
2840 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
2841 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
2842 } else if (ios->bus_width == bus_width_1) {
2843 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
2844 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
2846 panic("Invalid bus width: %d", ios->bus_width);
2848 if (ios->timing == bus_timing_hs &&
2849 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
2850 slot->hostctrl |= SDHCI_CTRL_HISPD;
2852 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
2853 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
2855 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
2856 SDHCI_RESET(slot->bus, slot,
2868 mmcio = &ccb->mmcio;
2871 /* if (slot->req != NULL) {
2879 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags,
2880 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0,
2881 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags : 0,
2882 mmcio->cmd.data != NULL ? mmcio->cmd.data->block_size : 0,
2883 mmcio->cmd.data != NULL ? mmcio->cmd.data->block_count : 0);
2885 if (mmcio->cmd.data != NULL) {
2886 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0)
2887 panic("data->len = %d, data->flags = %d -- something is b0rked",
2888 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags);
2890 slot->ccb = ccb;
2891 slot->flags = 0;