207 	uint32_t val32, wrk32;  in fsl_sdhci_read_1()  local
216 		val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET |  in fsl_sdhci_read_1()
223 			val32 |= SDHCI_CTRL_4BITBUS;  in fsl_sdhci_read_1()
226 			val32 |= SDHCI_CTRL_8BITBUS;  in fsl_sdhci_read_1()
237 			val32 |= SDHCI_CTRL_ADMA2;  in fsl_sdhci_read_1()
240 			val32 |= SDHCI_CTRL_ADMA264;  in fsl_sdhci_read_1()
243 		return val32;  in fsl_sdhci_read_1()
261 	uint32_t val32;  in fsl_sdhci_read_2()  local
298 		val32  = RD4(sc, SDHCI_INT_STATUS);  in fsl_sdhci_read_2()
299 		val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);  in fsl_sdhci_read_2()
300 		return (val32 ? 1 : 0);  in fsl_sdhci_read_2()
318 	uint32_t val32, wrk32;  in fsl_sdhci_read_4()  local
320 	val32 = RD4(sc, off);  in fsl_sdhci_read_4()
334 		val32 &= ~SDHCI_CAN_VDD_180;  in fsl_sdhci_read_4()
335 		val32 &= ~SDHCI_CAN_DO_SUSPEND;  in fsl_sdhci_read_4()
336 		val32 |= SDHCI_CAN_DO_8BITBUS;  in fsl_sdhci_read_4()
337 		return (val32);  in fsl_sdhci_read_4()
349 		wrk32 = val32;  in fsl_sdhci_read_4()
350 		val32 &= 0x000F0F07;  in fsl_sdhci_read_4()
351 		val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK;  in fsl_sdhci_read_4()
352 		val32 |= (wrk32 >> 9) & SDHCI_RETUNE_REQUEST;  in fsl_sdhci_read_4()
353 		return (val32);  in fsl_sdhci_read_4()
361 		return (val32 | sc->r1bfix_intmask);  in fsl_sdhci_read_4()
364 	return val32;  in fsl_sdhci_read_4()
380 	uint32_t val32;  in fsl_sdhci_write_1()  local
388 		val32 = RD4(sc, SDHC_PROT_CTRL);  in fsl_sdhci_write_1()
389 		val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK |  in fsl_sdhci_write_1()
391 		val32 |= (val & SDHCI_CTRL_LED);  in fsl_sdhci_write_1()
393 			val32 |= SDHC_PROT_WIDTH_8BIT;  in fsl_sdhci_write_1()
395 			val32 |= (val & SDHCI_CTRL_4BITBUS);  in fsl_sdhci_write_1()
396 		val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4;  in fsl_sdhci_write_1()
397 		val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD));  in fsl_sdhci_write_1()
398 		WR4(sc, SDHC_PROT_CTRL, val32);  in fsl_sdhci_write_1()
412 	val32 = RD4(sc, off & ~3);  in fsl_sdhci_write_1()
413 	val32 &= ~(0xff << (off & 3) * 8);  in fsl_sdhci_write_1()
414 	val32 |= (val << (off & 3) * 8);  in fsl_sdhci_write_1()
416 	WR4(sc, off & ~3, val32);  in fsl_sdhci_write_1()
423 	uint32_t val32;  in fsl_sdhci_write_2()  local
451 			val32 = RD4(sc, USDHC_MIX_CONTROL);  in fsl_sdhci_write_2()
452 			if ((val32 & MBAUTOCMD) == MBAUTOCMD)  in fsl_sdhci_write_2()
472 			val32 = RD4(sc, USDHC_MIX_CONTROL);  in fsl_sdhci_write_2()
473 			val32 &= ~0x3f;  in fsl_sdhci_write_2()
474 			val32 |= val & 0x37;  in fsl_sdhci_write_2()
476 			WR4(sc, USDHC_MIX_CONTROL, val32);  in fsl_sdhci_write_2()
492 	val32 = RD4(sc, off & ~3);  in fsl_sdhci_write_2()
493 	val32 &= ~(0xffff << (off & 3) * 8);  in fsl_sdhci_write_2()
494 	val32 |= ((val & 0xffff) << (off & 3) * 8);  in fsl_sdhci_write_2()
495 	WR4(sc, off & ~3, val32);	  in fsl_sdhci_write_2()
570 	uint32_t divisor, freq, prescale, val32;  in fsl_sdhc_set_clock()  local
572 	val32 = RD4(sc, SDHCI_CLOCK_CONTROL);  in fsl_sdhc_set_clock()
592 			WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHC_CLK_SDCLKEN);  in fsl_sdhc_set_clock()
641 	val32 &= ~(SDHC_CLK_DIVISOR_MASK | SDHC_CLK_PRESCALE_MASK);  in fsl_sdhc_set_clock()
642 	val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT;  in fsl_sdhc_set_clock()
643 	val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT;  in fsl_sdhc_set_clock()
644 	val32 |= SDHC_CLK_IPGEN;  in fsl_sdhc_set_clock()
645 	WR4(sc, SDHCI_CLOCK_CONTROL, val32);  in fsl_sdhc_set_clock()