190 RD4(struct fsl_sdhci_softc *sc, bus_size_t off)  in RD4()  argument
193 	return (bus_read_4(sc->mem_res, off));  in RD4()
197 WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val)  in WR4()  argument
200 	bus_write_4(sc->mem_res, off, val);  in WR4()
204 fsl_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)  in fsl_sdhci_read_1()  argument
214 	if (off == SDHCI_HOST_CONTROL) {  in fsl_sdhci_read_1()
250 	if (off == SDHCI_POWER_CONTROL) {  in fsl_sdhci_read_1()
254 	return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);  in fsl_sdhci_read_1()
258 fsl_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)  in fsl_sdhci_read_2()  argument
268 		if (off == SDHCI_HOST_VERSION) {  in fsl_sdhci_read_2()
275 		if (off == SDHCI_TRANSFER_MODE)  in fsl_sdhci_read_2()
285 		if (off == SDHCI_TRANSFER_MODE) {  in fsl_sdhci_read_2()
287 		} else if (off == SDHCI_COMMAND_FLAGS) {  in fsl_sdhci_read_2()
297 	if (off == SDHCI_SLOT_INT_STATUS) {  in fsl_sdhci_read_2()
307 	if (off == SDHCI_CLOCK_CONTROL) {  in fsl_sdhci_read_2()
311 	return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);  in fsl_sdhci_read_2()
315 fsl_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)  in fsl_sdhci_read_4()  argument
320 	val32 = RD4(sc, off);  in fsl_sdhci_read_4()
333 	if (off == SDHCI_CAPABILITIES) {  in fsl_sdhci_read_4()
348 	if (off == SDHCI_PRESENT_STATE) {  in fsl_sdhci_read_4()
360 	if (off == SDHCI_INT_STATUS) {  in fsl_sdhci_read_4()
368 fsl_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,  in fsl_sdhci_read_multi_4()  argument
373 	bus_read_multi_4(sc->mem_res, off, data, count);  in fsl_sdhci_read_multi_4()
377 fsl_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)  in fsl_sdhci_write_1()  argument
387 	if (off == SDHCI_HOST_CONTROL) {  in fsl_sdhci_write_1()
403 	if (off == SDHCI_POWER_CONTROL) {  in fsl_sdhci_write_1()
408 	if (off == SDHCI_SOFTWARE_RESET)  in fsl_sdhci_write_1()
412 	val32 = RD4(sc, off & ~3);  in fsl_sdhci_write_1()
413 	val32 &= ~(0xff << (off & 3) * 8);  in fsl_sdhci_write_1()
414 	val32 |= (val << (off & 3) * 8);  in fsl_sdhci_write_1()
416 	WR4(sc, off & ~3, val32);  in fsl_sdhci_write_1()
420 fsl_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)  in fsl_sdhci_write_2()  argument
429 	if (off == SDHCI_CLOCK_CONTROL) {  in fsl_sdhci_write_2()
448 	if (off == SDHCI_COMMAND_FLAGS) {  in fsl_sdhci_write_2()
471 		if (off == SDHCI_TRANSFER_MODE) {  in fsl_sdhci_write_2()
480 		if (off == SDHCI_TRANSFER_MODE) {  in fsl_sdhci_write_2()
484 		} else if (off == SDHCI_COMMAND_FLAGS) {  in fsl_sdhci_write_2()
492 	val32 = RD4(sc, off & ~3);  in fsl_sdhci_write_2()
493 	val32 &= ~(0xffff << (off & 3) * 8);  in fsl_sdhci_write_2()
494 	val32 |= ((val & 0xffff) << (off & 3) * 8);  in fsl_sdhci_write_2()
495 	WR4(sc, off & ~3, val32);	  in fsl_sdhci_write_2()
499 fsl_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)  in fsl_sdhci_write_4()  argument
504 	if (off == SDHCI_INT_STATUS) {  in fsl_sdhci_write_4()
508 	WR4(sc, off, val);  in fsl_sdhci_write_4()
512 fsl_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,  in fsl_sdhci_write_multi_4()  argument
517 	bus_write_multi_4(sc->mem_res, off, data, count);  in fsl_sdhci_write_multi_4()