Lines Matching full:usdhc

31  * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs).
161  * The clock enable bits exist in different registers for ESDHC vs USDHC, but
177 	{"fsl,imx6q-usdhc",	HWTYPE_USDHC},
178 	{"fsl,imx6sl-usdhc",	HWTYPE_USDHC},
265 		 * The USDHC hardware has nothing in the version register, but  in fsl_sdhci_read_2()
272 		 * The USDHC hardware moved the transfer mode bits to the mixed  in fsl_sdhci_read_2()
427 	 * that can handle the ESDHC versus USDHC differences.  in fsl_sdhci_write_2()
464 	 * The USDHC hardware moved the transfer mode bits to mixed control; we  in fsl_sdhci_write_2()
548 	 * here). On USDHC and QorIQ ESDHC hardware there is a force-on bit, but  in fsl_sdhc_get_clock()
600 		 * The USDHC hardware provides only "force always on" control  in fsl_sdhc_set_clock()
604 		 * now, otherwise we decode the requested frequency.  USDHC  in fsl_sdhc_set_clock()
952 		device_set_desc(dev, "Freescale uSDHC controller");  in fsl_sdhci_probe()