Lines Matching +full:int +full:- +full:clock +full:- +full:stable +full:- +full:broken
1 /*-
105 * Freescale-specific registers, or in some cases the layout of bits within the
106 * sdhci-defined register is different on Freescale. These names all begin with
112 #define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */
161 * The clock enable bits exist in different registers for ESDHC vs USDHC, but
163 * standard sdhci clock register, but in different bit positions and meanings
177 {"fsl,imx6q-usdhc", HWTYPE_USDHC},
178 {"fsl,imx6sl-usdhc", HWTYPE_USDHC},
179 {"fsl,imx53-esdhc", HWTYPE_ESDHC},
180 {"fsl,imx51-esdhc", HWTYPE_ESDHC},
193 return (bus_read_4(sc->mem_res, off)); in RD4()
200 bus_write_4(sc->mem_res, off, val); in WR4()
263 if (sc->hwtype == HWTYPE_USDHC) { in fsl_sdhci_read_2()
278 } else if (sc->hwtype == HWTYPE_ESDHC) { in fsl_sdhci_read_2()
280 * The ESDHC hardware has the typical 32-bit combined "command in fsl_sdhci_read_2()
286 return (sc->cmd_and_mode & 0x0000ffff); in fsl_sdhci_read_2()
288 return (sc->cmd_and_mode >> 16); in fsl_sdhci_read_2()
304 * Clock bits are scattered into various registers which differ by in fsl_sdhci_read_2()
323 * The hardware leaves the base clock frequency out of the capabilities in fsl_sdhci_read_4()
324 * register, but we filled it in by setting slot->max_clk at attach time in fsl_sdhci_read_4()
326 * in an sdhci 2.0 capabliities register. The timeout clock is the same in fsl_sdhci_read_4()
344 * masks out some Freescale-specific bits in locations defined as in fsl_sdhci_read_4()
361 return (val32 | sc->r1bfix_intmask); in fsl_sdhci_read_4()
373 bus_read_multi_4(sc->mem_res, off, data, count); in fsl_sdhci_read_multi_4()
426 * The clock control stuff is complex enough to have its own function in fsl_sdhci_write_2()
438 * - R1B response with no data transfer should generate a DATA_END (aka in fsl_sdhci_write_2()
442 * - R1B response after Auto-CMD12 appears to not work, even though in fsl_sdhci_write_2()
453 sc->r1bfix_type = R1BFIX_AC12; in fsl_sdhci_write_2()
456 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); in fsl_sdhci_write_2()
457 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); in fsl_sdhci_write_2()
458 sc->r1bfix_type = R1BFIX_NODATA; in fsl_sdhci_write_2()
466 * typical combined cmd-and-mode register that allows only 32-bit in fsl_sdhci_write_2()
470 if (sc->hwtype == HWTYPE_USDHC) { in fsl_sdhci_write_2()
479 } else if (sc->hwtype == HWTYPE_ESDHC) { in fsl_sdhci_write_2()
481 sc->cmd_and_mode = in fsl_sdhci_write_2()
482 (sc->cmd_and_mode & 0xffff0000) | val; in fsl_sdhci_write_2()
485 sc->cmd_and_mode = in fsl_sdhci_write_2()
486 (sc->cmd_and_mode & 0xffff) | (val << 16); in fsl_sdhci_write_2()
487 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); in fsl_sdhci_write_2()
505 sc->r1bfix_intmask &= ~val; in fsl_sdhci_write_4()
517 bus_write_multi_4(sc->mem_res, off, data, count); in fsl_sdhci_write_multi_4()
526 * Whenever the sdhci driver writes the clock register we save a in fsl_sdhc_get_clock()
530 * those bits, and mix in the clock status and enable bits that come in fsl_sdhc_get_clock()
533 val = sc->sdclockreg_freq_bits; in fsl_sdhc_get_clock()
536 * The internal clock is always enabled (actually, the hardware manages in fsl_sdhc_get_clock()
537 * it). Whether the internal clock is stable yet after a frequency in fsl_sdhc_get_clock()
538 * change comes from the present-state register on both hardware types. in fsl_sdhc_get_clock()
545 * On i.MX ESDHC hardware the card bus clock enable is in the usual in fsl_sdhc_get_clock()
548 * here). On USDHC and QorIQ ESDHC hardware there is a force-on bit, but in fsl_sdhc_get_clock()
549 * no force-off for the card bus clock (the hardware runs the clock when in fsl_sdhc_get_clock()
550 * transfers are active no matter what), so we always say the clock is in fsl_sdhc_get_clock()
555 if (sc->hwtype == HWTYPE_ESDHC) { in fsl_sdhc_get_clock()
575 * Save the frequency-setting bits in SDHCI format so that we can play in fsl_sdhc_set_clock()
579 sc->sdclockreg_freq_bits = val & SDHCI_DIVIDERS_MASK; in fsl_sdhc_set_clock()
580 if (sc->hwtype == HWTYPE_ESDHC) { in fsl_sdhc_set_clock()
583 * start and stop the sd bus clock. If the enable bit is not in fsl_sdhc_set_clock()
584 * set, turn off the clock in hardware and we're done, otherwise in fsl_sdhc_set_clock()
586 * the sdhci driver will use the original 8-bit divisor field in fsl_sdhc_set_clock()
597 freq = sc->baseclk_hz >> ffs(divisor); in fsl_sdhc_set_clock()
601 * over the sd bus clock, but no way to turn it off. (If a cmd in fsl_sdhc_set_clock()
602 * or data transfer is in progress the clock is on, otherwise it in fsl_sdhc_set_clock()
603 * is off.) If the clock is being disabled, we can just return in fsl_sdhc_set_clock()
605 * hardware is sdhci 3.0; the sdhci driver will use a 10-bit in fsl_sdhc_set_clock()
614 freq = sc->baseclk_hz; in fsl_sdhc_set_clock()
616 freq = sc->baseclk_hz / (2 * divisor); in fsl_sdhc_set_clock()
622 for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16);) in fsl_sdhc_set_clock()
625 for (divisor = 1; freq < sc->baseclk_hz / (prescale * divisor);) in fsl_sdhc_set_clock()
629 device_printf(sc->dev, in fsl_sdhc_set_clock()
631 freq, sc->baseclk_hz / (prescale * divisor), sc->baseclk_hz, in fsl_sdhc_set_clock()
636 * Adjust to zero-based values, and store them to the hardware. in fsl_sdhc_set_clock()
639 divisor -= 1; in fsl_sdhc_set_clock()
653 mtx_assert(&sc->slot.mtx, MA_OWNED); in fsl_sdhci_r1bfix_is_wait_done()
664 if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) { in fsl_sdhci_r1bfix_is_wait_done()
665 callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0, in fsl_sdhci_r1bfix_is_wait_done()
674 * of fix needed was on a command-without-data we also now add in the in fsl_sdhci_r1bfix_is_wait_done()
678 sc->r1bfix_intmask |= SDHCI_INT_DATA_TIMEOUT; in fsl_sdhci_r1bfix_is_wait_done()
680 sc->r1bfix_intmask |= SDHCI_INT_DATA_END; in fsl_sdhci_r1bfix_is_wait_done()
681 if (sc->r1bfix_type == R1BFIX_NODATA) in fsl_sdhci_r1bfix_is_wait_done()
682 sc->r1bfix_intmask |= SDHCI_INT_RESPONSE; in fsl_sdhci_r1bfix_is_wait_done()
685 sc->r1bfix_type = R1BFIX_NONE; in fsl_sdhci_r1bfix_is_wait_done()
695 mtx_lock(&sc->slot.mtx); in fsl_sdhci_r1bfix_func()
697 mtx_unlock(&sc->slot.mtx); in fsl_sdhci_r1bfix_func()
699 sdhci_generic_intr(&sc->slot); in fsl_sdhci_r1bfix_func()
708 mtx_lock(&sc->slot.mtx); in fsl_sdhci_intr()
717 * not, then the wait_done routine will schedule a callout to re-check in fsl_sdhci_intr()
725 * cards tend to take 10-20ms for a long-running command such as a write in fsl_sdhci_intr()
728 switch (sc->r1bfix_type) { in fsl_sdhci_intr()
740 sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS; in fsl_sdhci_intr()
743 bus_barrier(sc->mem_res, SDHCI_INT_STATUS, 4, in fsl_sdhci_intr()
748 mtx_unlock(&sc->slot.mtx); in fsl_sdhci_intr()
749 sdhci_generic_intr(&sc->slot); in fsl_sdhci_intr()
752 static int
757 return (sdhci_fdt_gpio_get_readonly(sc->gpio)); in fsl_sdhci_get_ro()
765 return (sdhci_fdt_gpio_get_present(sc->gpio)); in fsl_sdhci_get_card_present()
773 uint32_t clock; in fsl_sdhci_get_platform_clock() local
778 if((OF_getprop(node, "clock-frequency", (void *)&clock, in fsl_sdhci_get_platform_clock()
779 sizeof(clock)) <= 0) || (clock == 0)) { in fsl_sdhci_get_platform_clock()
780 clock = mpc85xx_get_system_clock(); in fsl_sdhci_get_platform_clock()
782 if (clock == 0) { in fsl_sdhci_get_platform_clock()
791 device_printf(dev, "Acquired clock: %d from DTS\n", clock); in fsl_sdhci_get_platform_clock()
793 return (clock); in fsl_sdhci_get_platform_clock()
797 static int
802 if (sc->gpio != NULL) in fsl_sdhci_detach()
803 sdhci_fdt_gpio_teardown(sc->gpio); in fsl_sdhci_detach()
805 callout_drain(&sc->r1bfix_callout); in fsl_sdhci_detach()
807 if (sc->slot_init_done) in fsl_sdhci_detach()
808 sdhci_cleanup_slot(&sc->slot); in fsl_sdhci_detach()
810 if (sc->intr_cookie != NULL) in fsl_sdhci_detach()
811 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); in fsl_sdhci_detach()
812 if (sc->irq_res != NULL) in fsl_sdhci_detach()
814 rman_get_rid(sc->irq_res), sc->irq_res); in fsl_sdhci_detach()
816 if (sc->mem_res != NULL) { in fsl_sdhci_detach()
818 rman_get_rid(sc->mem_res), sc->mem_res); in fsl_sdhci_detach()
824 static int
828 int rid, err; in fsl_sdhci_attach()
834 sc->dev = dev; in fsl_sdhci_attach()
836 callout_init(&sc->r1bfix_callout, 1); in fsl_sdhci_attach()
838 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; in fsl_sdhci_attach()
839 if (sc->hwtype == HWTYPE_NONE) in fsl_sdhci_attach()
843 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in fsl_sdhci_attach()
845 if (!sc->mem_res) { in fsl_sdhci_attach()
852 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, in fsl_sdhci_attach()
854 if (!sc->irq_res) { in fsl_sdhci_attach()
860 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, in fsl_sdhci_attach()
861 NULL, fsl_sdhci_intr, sc, &sc->intr_cookie)) { in fsl_sdhci_attach()
867 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; in fsl_sdhci_attach()
870 * DMA is not really broken, I just haven't implemented it yet. in fsl_sdhci_attach()
872 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; in fsl_sdhci_attach()
879 * re-check the status and potentially wait for more data. The main in fsl_sdhci_attach()
891 if (ofw_bus_is_compatible(dev, "fsl,p1022-esdhc")) in fsl_sdhci_attach()
901 sc->baseclk_hz = fsl_sdhci_get_platform_clock(dev); in fsl_sdhci_attach()
903 sc->baseclk_hz = imx_ccm_sdhci_hz(); in fsl_sdhci_attach()
905 sc->slot.max_clk = sc->baseclk_hz; in fsl_sdhci_attach()
911 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot); in fsl_sdhci_attach()
915 /* Default to big-endian on powerpc */ in fsl_sdhci_attach()
918 if (OF_hasprop(node, "little-endian")) in fsl_sdhci_attach()
925 sdhci_init_slot(dev, &sc->slot, 0); in fsl_sdhci_attach()
926 sc->slot_init_done = true; in fsl_sdhci_attach()
931 sdhci_start_slot(&sc->slot); in fsl_sdhci_attach()
940 static int
947 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { in fsl_sdhci_probe()