240 		    (sc->sc_config.rd_offset * nrdescs * sizeof(uint32_t)));  in safexcel_rdr_intr()
321 	sc->sc_config.aic_rings = i;  in safexcel_configure()
322 	if (sc->sc_config.aic_rings == 0)  in safexcel_configure()
334 	sc->sc_config.hdw =  in safexcel_configure()
336 	mask = (1 << sc->sc_config.hdw) - 1;  in safexcel_configure()
338 	sc->sc_config.rings = reg & SAFEXCEL_N_RINGS_MASK;  in safexcel_configure()
340 	sc->sc_config.rings = MIN(sc->sc_config.rings, sc->sc_config.aic_rings);  in safexcel_configure()
342 	sc->sc_config.pes = (reg & pemask) >> SAFEXCEL_N_PES_OFFSET;  in safexcel_configure()
344 	sc->sc_config.cd_size =  in safexcel_configure()
346 	sc->sc_config.cd_offset = (sc->sc_config.cd_size + mask) & ~mask;  in safexcel_configure()
348 	sc->sc_config.rd_size =  in safexcel_configure()
350 	sc->sc_config.rd_offset = (sc->sc_config.rd_size + mask) & ~mask;  in safexcel_configure()
352 	sc->sc_config.atok_offset =  in safexcel_configure()
485 	for (i = 0; i < sc->sc_config.rings; i++) {  in safexcel_hw_prepare_rings()
516 		    SAFEXCEL_RING_SIZE * sc->sc_config.cd_offset *  in safexcel_hw_prepare_rings()
545 		    SAFEXCEL_RING_SIZE * sc->sc_config.rd_offset *  in safexcel_hw_prepare_rings()
557 	mask = (1 << sc->sc_config.hdw) - 1;  in safexcel_hw_setup_rings()
558 	cd_size_rnd = (sc->sc_config.cd_size + mask) >> sc->sc_config.hdw;  in safexcel_hw_setup_rings()
561 	rd_size_rnd = (val + mask) >> sc->sc_config.hdw;  in safexcel_hw_setup_rings()
563 	for (i = 0; i < sc->sc_config.rings; i++) {  in safexcel_hw_setup_rings()
581 		    (sc->sc_config.cd_offset << SAFEXCEL_xDR_DESC_xD_OFFSET) |  in safexcel_hw_setup_rings()
582 		    sc->sc_config.cd_size);  in safexcel_hw_setup_rings()
586 		    ((SAFEXCEL_FETCH_COUNT * (cd_size_rnd << sc->sc_config.hdw)) <<  in safexcel_hw_setup_rings()
588 		    (SAFEXCEL_FETCH_COUNT * sc->sc_config.cd_offset));  in safexcel_hw_setup_rings()
616 		    (sc->sc_config.rd_offset << SAFEXCEL_xDR_DESC_xD_OFFSET) |  in safexcel_hw_setup_rings()
617 		    sc->sc_config.rd_size);  in safexcel_hw_setup_rings()
621 		    ((SAFEXCEL_FETCH_COUNT * (rd_size_rnd << sc->sc_config.hdw)) <<  in safexcel_hw_setup_rings()
623 		    (SAFEXCEL_FETCH_COUNT * sc->sc_config.rd_offset));  in safexcel_hw_setup_rings()
650 	for (i = 0; i < sc->sc_config.rings; i++) {  in safexcel_hw_reset_rings()
729 	for (ring_mask = 0, i = 0; i < sc->sc_config.rings; i++) {  in safexcel_enable_pe_engine()
777 	    nrdesc * sc->sc_config.rd_offset * sizeof(uint32_t));  in safexcel_execute()
780 	    ncdesc * sc->sc_config.cd_offset * sizeof(uint32_t));  in safexcel_execute()
793 	for (i = 0; i < sc->sc_config.rings; i++) {  in safexcel_init_rings()
807 			    sc->sc_config.atok_offset * j;  in safexcel_init_rings()
893 	for (i = 0; i < sc->sc_config.rings; i++) {  in safexcel_dma_free_rings()
910 	for (i = 0; i < sc->sc_config.rings; i++) {  in safexcel_dma_init()
931 		size = sizeof(uint32_t) * sc->sc_config.cd_offset *  in safexcel_dma_init()
944 		size = (bus_size_t)sc->sc_config.atok_offset *  in safexcel_dma_init()
954 		size = sizeof(uint32_t) * sc->sc_config.rd_offset *  in safexcel_dma_init()
999 	for (pe = 0; pe < sc->sc_config.pes; pe++) {  in safexcel_init_hw()
1021 	for (pe = 0; pe < sc->sc_config.pes; pe++)  in safexcel_init_hw()
1177 	for (ringidx = 0; ringidx < sc->sc_config.rings; ringidx++) {  in safexcel_attach()
1262 	for (ringidx = 0; ringidx < sc->sc_config.rings; ringidx++) {  in safexcel_detach()
1928 		    sc->sc_config.atok_offset *  in safexcel_set_token()
2538 	ring = &sc->sc_ring[curcpu % sc->sc_config.rings];  in safexcel_process()