Lines Matching +full:hdr +full:- +full:engine
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
33 * Register definitions for SafeNet SafeXcel-1141 crypto device.
47 #define SAFE_PE_SRC 0x0004 /* Packet Engine Source */
48 #define SAFE_PE_DST 0x0008 /* Packet Engine Destination */
49 #define SAFE_PE_SA 0x000c /* Packet Engine SA */
50 #define SAFE_PE_LEN 0x0010 /* Packet Engine Length */
51 #define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */
52 #define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */
53 #define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */
54 #define SAFE_PE_RDRBASE 0x004c /* Packet Engine Result Ring Base */
55 #define SAFE_PE_RINGCFG 0x0050 /* Packet Engine Ring Configuration */
56 #define SAFE_PE_RINGPOLL 0x0054 /* Packet Engine Ring Poll */
57 #define SAFE_PE_IRNGSTAT 0x0058 /* Packet Engine Internal Ring Status */
58 #define SAFE_PE_ERNGSTAT 0x005c /* Packet Engine External Ring Status */
59 #define SAFE_PE_IOTHRESH 0x0060 /* Packet Engine I/O Threshold */
60 #define SAFE_PE_GRNGBASE 0x0064 /* Packet Engine Gather Ring Base */
61 #define SAFE_PE_SRNGBASE 0x0068 /* Packet Engine Scatter Ring Base */
62 #define SAFE_PE_PARTSIZE 0x006c /* Packet Engine Particlar Ring Size */
63 #define SAFE_PE_PARTCFG 0x0070 /* Packet Engine Particle Ring Config */
68 #define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */
69 #define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */
110 #define SAFE_PE_CSR_NXTHDR 0x0000ff00 /* next hdr value for IPsec */
129 #define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */
130 #define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */
131 #define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */
132 #define SAFE_PE_CSR_PAD_128 0x40000000 /* pad to 128-byte boundary */
133 #define SAFE_PE_CSR_PAD_256 0x80000000 /* pad to 256-byte boundary */
162 #define SAFE_HI_CFG_AUTOCLR 0x00000002 /* auto-clear pulse interrupt */
164 #define SAFE_ENDIAN_PASS 0x000000e4 /* straight pass-thru */
165 #define SAFE_ENDIAN_SWAB 0x0000001b /* swap bytes in 32-bit word */
167 #define SAFE_PE_DMACFG_PERESET 0x00000001 /* reset packet engine */
171 #define SAFE_PE_DMACFG_PEMODE 0x00000100 /* packet engine mode */
193 #define SAFE_PE_DMASTAT_CRYPTO 0x00000100 /* crypto engine timeout */
197 #define SAFE_PE_DMASTAT_PEISIZE 0x003ff000 /* PE input size:32-bit words */
198 #define SAFE_PE_DMASTAT_PEOSIZE 0xffc00000 /* PE out. size:32-bit words */
242 #define SAFE_DEVINFO_SHA1 0x00002000 /* SHA-1 support present */
245 #define SAFE_DEVINFO_SARAM 0x00100000 /* on-chip SA RAM present */
259 #define SAFE_PK_FUNC_LSHIFT 0x00000040 /* Left-shift function */
260 #define SAFE_PK_FUNC_RSHIFT 0x00000080 /* Right-shift function */
264 #define SAFE_PK_FUNC_EXP16 0x00002000 /* Exponentiate (4-bit ACT) */
265 #define SAFE_PK_FUNC_EXP4 0x00004000 /* Exponentiate (2-bit ACT) */
269 #define SAFE_RNG_CTRL_PRE_LFSR 0x00000001 /* enable output pre-LFSR */
281 * Packet engine descriptor. Note that d_csr is a copy of the
288 u_int32_t d_csr; /* per-packet control/status */
312 * required for each operation processed by the packet engine.
334 #define SAFE_SA_CMD0_OP_BOTH 0x00000001 /* encrypt-hash/hash-decrypto */
335 #define SAFE_SA_CMD0_OP_HASH 0x00000003 /* hash (outbound-only) */
356 #define SAFE_SA_CMD0_SHA1 0x00001000 /* SHA-1 hash algorithm */
390 #define SAFE_SA_CMD1_64BIT 0x00000000 /* 64-bit crypto feedback */
391 #define SAFE_SA_CMD1_8BIT 0x00000400 /* 8-bit crypto feedback */
392 #define SAFE_SA_CMD1_1BIT 0x00000800 /* 1-bit crypto feedback */
393 #define SAFE_SA_CMD1_128BIT 0x00000c00 /* 128-bit crypto feedback */
400 #define SAFE_SA_CMD1_AES128 0x02000000 /* 128-bit AES key */
401 #define SAFE_SA_CMD1_AES192 0x03000000 /* 192-bit AES key */
402 #define SAFE_SA_CMD1_AES256 0x04000000 /* 256-bit AES key */