Lines Matching +full:scatter +full:- +full:gather
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
33 * Register definitions for SafeNet SafeXcel-1141 crypto device.
60 #define SAFE_PE_GRNGBASE 0x0064 /* Packet Engine Gather Ring Base */
61 #define SAFE_PE_SRNGBASE 0x0068 /* Packet Engine Scatter Ring Base */
68 #define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */
69 #define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */
129 #define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */
130 #define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */
131 #define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */
132 #define SAFE_PE_CSR_PAD_128 0x40000000 /* pad to 128-byte boundary */
133 #define SAFE_PE_CSR_PAD_256 0x80000000 /* pad to 256-byte boundary */
162 #define SAFE_HI_CFG_AUTOCLR 0x00000002 /* auto-clear pulse interrupt */
164 #define SAFE_ENDIAN_PASS 0x000000e4 /* straight pass-thru */
165 #define SAFE_ENDIAN_SWAB 0x0000001b /* swap bytes in 32-bit word */
169 #define SAFE_PE_DMACFG_SGRESET 0x00000004 /* reset scatter/gather cache */
174 #define SAFE_PE_DMACFG_GPRBID 0x00003000 /* gather particle ring busid */
175 #define SAFE_PE_DMACFG_GPRPCI 0x00001000 /* PCI gather particle ring */
176 #define SAFE_PE_DMACFG_SPRBID 0x0000c000 /* scatter part. ring busid */
177 #define SAFE_PE_DMACFG_SPRPCI 0x00004000 /* PCI scatter part. ring */
197 #define SAFE_PE_DMASTAT_PEISIZE 0x003ff000 /* PE input size:32-bit words */
198 #define SAFE_PE_DMASTAT_PEOSIZE 0xffc00000 /* PE out. size:32-bit words */
216 #define SAFE_PE_PARTCFG_SIZE 0x0000ffff /* scatter particle size */
217 #define SAFE_PE_PARTCFG_GBURST 0x00030000 /* gather particle burst */
222 #define SAFE_PE_PARTCFG_SBURST 0x000c0000 /* scatter particle burst */
228 #define SAFE_PE_PARTSIZE_SCAT 0xffff0000 /* scatter particle ring size */
229 #define SAFE_PE_PARTSIZE_GATH 0x0000ffff /* gather particle ring size */
242 #define SAFE_DEVINFO_SHA1 0x00002000 /* SHA-1 support present */
245 #define SAFE_DEVINFO_SARAM 0x00100000 /* on-chip SA RAM present */
259 #define SAFE_PK_FUNC_LSHIFT 0x00000040 /* Left-shift function */
260 #define SAFE_PK_FUNC_RSHIFT 0x00000080 /* Right-shift function */
264 #define SAFE_PK_FUNC_EXP16 0x00002000 /* Exponentiate (4-bit ACT) */
265 #define SAFE_PK_FUNC_EXP4 0x00004000 /* Exponentiate (2-bit ACT) */
269 #define SAFE_RNG_CTRL_PRE_LFSR 0x00000001 /* enable output pre-LFSR */
285 * list of ``particle descriptors'' when using scatter/gather i/o.
288 u_int32_t d_csr; /* per-packet control/status */
296 * Scatter/Gather particle descriptor.
298 * NB: scatter descriptors do not specify a size; this is fixed
334 #define SAFE_SA_CMD0_OP_BOTH 0x00000001 /* encrypt-hash/hash-decrypto */
335 #define SAFE_SA_CMD0_OP_HASH 0x00000003 /* hash (outbound-only) */
356 #define SAFE_SA_CMD0_SHA1 0x00001000 /* SHA-1 hash algorithm */
373 #define SAFE_SA_CMD0_IGATHER 0x40000000 /* input gather */
374 #define SAFE_SA_CMD0_OSCATTER 0x80000000 /* output scatter */
390 #define SAFE_SA_CMD1_64BIT 0x00000000 /* 64-bit crypto feedback */
391 #define SAFE_SA_CMD1_8BIT 0x00000400 /* 8-bit crypto feedback */
392 #define SAFE_SA_CMD1_1BIT 0x00000800 /* 1-bit crypto feedback */
393 #define SAFE_SA_CMD1_128BIT 0x00000c00 /* 128-bit crypto feedback */
400 #define SAFE_SA_CMD1_AES128 0x02000000 /* 128-bit AES key */
401 #define SAFE_SA_CMD1_AES192 0x03000000 /* 192-bit AES key */
402 #define SAFE_SA_CMD1_AES256 0x04000000 /* 256-bit AES key */