Lines Matching +full:0 +full:xc40
36 #define R12A_SDIO_CTRL 0x070
37 #define R12A_RF_B_CTRL 0x076
39 #define R12A_RXDMA_PRO 0x290
40 #define R12A_EARLY_MODE_CONTROL 0x2bc
42 #define R12A_TXPKT_EMPTY 0x41a
43 #define R12A_ARFR_5G(i) (0x444 + (i) * 8)
44 #define R12A_CCK_CHECK 0x454
45 #define R12A_AMPDU_MAX_TIME 0x456
47 #define R12A_DATA_SEC 0x483
48 #define R12A_DATA_SEC_TXSC_20M_M 0x0000000f
49 #define R12A_DATA_SEC_TXSC_20M_S 0
50 #define R12A_DATA_SEC_TXSC_40M_M 0x000000f0
52 #define R12A_ARFR_2G(i) (0x48c + (i) * 8)
53 #define R12A_HT_SINGLE_AMPDU 0x4c7
56 #define R12A_MAC_PHY_CRYSTALCAP_M 0x7ff80000
60 #define R12A_LEDCFG2_ENA 0x20
63 #define R12A_DMA_MODE 0x02
64 #define R12A_BURST_CNT_M 0x0c
66 #define R12A_BURST_SZ_M 0x30
68 #define R12A_BURST_SZ_USB3 0
73 #define R12A_CCK_CHECK_BCN1 0x20
74 #define R12A_CCK_CHECK_5GHZ 0x80
77 #define R12A_DATA_SEC_NO_EXT 0x00
78 #define R12A_DATA_SEC_PRIM_UP_20 0x01
79 #define R12A_DATA_SEC_PRIM_DOWN_20 0x02
80 #define R12A_DATA_SEC_PRIM_UPPER_20 0x03
81 #define R12A_DATA_SEC_PRIM_LOWER_20 0x04
82 #define R12A_DATA_SEC_PRIM_UP_40 0x09
83 #define R12A_DATA_SEC_PRIM_DOWN_40 0x0a
86 #define R12A_HT_SINGLE_AMPDU_PKT_ENA 0x80
89 #define R12A_RCR_DIS_CHK_14 0x00200000
90 #define R12A_RCR_TCP_OFFLD_EN 0x02000000
91 #define R12A_RCR_VHT_ACK 0x04000000
96 #define R12A_CCK_RPT_FORMAT 0x804
97 #define R12A_OFDMCCK_EN 0x808
99 #define R12A_TX_PATH 0x80c
100 #define R12A_TXAGC_TABLE_SELECT 0x82c
101 #define R12A_PWED_TH 0x830
102 #define R12A_BW_INDICATION 0x834
103 #define R12A_CCA_ON_SEC 0x838
104 #define R12A_L1_PEAK_TH 0x848
105 #define R12A_FC_AREA 0x860
106 #define R12A_RFMOD 0x8ac
107 #define R12A_HSSI_PARAM2 0x8b0
108 #define R12A_ADC_BUF_CLK 0x8c4
109 #define R12A_ANTSEL_SW 0x900
110 #define R12A_SINGLETONE_CONT_TX 0x914
111 #define R12A_CCK_RX_PATH 0xa04
112 #define R12A_HSSI_PARAM1(chain) (0xc00 + (chain) * 0x200)
113 #define R12A_TX_SCALE(chain) (0xc1c + (chain) * 0x200)
114 #define R12A_TXAGC_CCK11_1(chain) (0xc20 + (chain) * 0x200)
115 #define R12A_TXAGC_OFDM18_6(chain) (0xc24 + (chain) * 0x200)
116 #define R12A_TXAGC_OFDM54_24(chain) (0xc28 + (chain) * 0x200)
117 #define R12A_TXAGC_MCS3_0(chain) (0xc2c + (chain) * 0x200)
118 #define R12A_TXAGC_MCS7_4(chain) (0xc30 + (chain) * 0x200)
119 #define R12A_TXAGC_MCS11_8(chain) (0xc34 + (chain) * 0x200)
120 #define R12A_TXAGC_MCS15_12(chain) (0xc38 + (chain) * 0x200)
121 #define R12A_TXAGC_NSS1IX3_1IX0(chain) (0xc3c + (chain) * 0x200)
122 #define R12A_TXAGC_NSS1IX7_1IX4(chain) (0xc40 + (chain) * 0x200)
123 #define R12A_TXAGC_NSS2IX1_1IX8(chain) (0xc44 + (chain) * 0x200)
124 #define R12A_TXAGC_NSS2IX5_2IX2(chain) (0xc48 + (chain) * 0x200)
125 #define R12A_TXAGC_NSS2IX9_2IX6(chain) (0xc4c + (chain) * 0x200)
126 #define R12A_INITIAL_GAIN(chain) (0xc50 + (chain) * 0x200)
127 #define R12A_TX_PWR_TRAINING(chain) (0xc54 + (chain) * 0x200)
128 #define R12A_AFE_POWER_1(chain) (0xc60 + (chain) * 0x200)
129 #define R12A_AFE_POWER_2(chain) (0xc64 + (chain) * 0x200)
130 #define R12A_SLEEP_NAV(chain) (0xc80 + (chain) * 0x200)
131 #define R12A_PMPD(chain) (0xc84 + (chain) * 0x200)
132 #define R12A_LSSI_PARAM(chain) (0xc90 + (chain) * 0x200)
133 #define R12A_RFE_PINMUX(chain) (0xcb0 + (chain) * 0x200)
134 #define R12A_RFE_INV(chain) (0xcb4 + (chain) * 0x200)
135 #define R12A_RFE(chain) (0xcb8 + (chain) * 0x200)
136 #define R12A_HSPI_READBACK(chain) (0xd04 + (chain) * 0x40)
137 #define R12A_LSSI_READBACK(chain) (0xd08 + (chain) * 0x40)
140 #define R12A_CCK_RPT_FORMAT_HIPWR 0x00010000
143 #define R12A_OFDMCCK_EN_CCK 0x10000000
144 #define R12A_OFDMCCK_EN_OFDM 0x20000000
147 #define R12A_CCA_ON_SEC_EXT_CHAN_M 0xf0000000
151 #define R12A_RFE_PINMUX_PA_A_MASK 0x000000f0
152 #define R12A_RFE_PINMUX_LNA_MASK 0x0000f000
155 #define R12A_RFMOD_EXT_CHAN_M 0x3C
159 #define R12A_HSSI_PARAM2_READ_ADDR_MASK 0xff
162 #define R12A_HSSI_PARAM1_PI 0x00000004
165 #define R12A_TX_SCALE_SWING_M 0xffe00000
169 #define R12A_TXAGC_CCK1_M 0x000000ff
170 #define R12A_TXAGC_CCK1_S 0
171 #define R12A_TXAGC_CCK2_M 0x0000ff00
173 #define R12A_TXAGC_CCK55_M 0x00ff0000
175 #define R12A_TXAGC_CCK11_M 0xff000000
179 #define R12A_TXAGC_OFDM06_M 0x000000ff
180 #define R12A_TXAGC_OFDM06_S 0
181 #define R12A_TXAGC_OFDM09_M 0x0000ff00
183 #define R12A_TXAGC_OFDM12_M 0x00ff0000
185 #define R12A_TXAGC_OFDM18_M 0xff000000
189 #define R12A_TXAGC_OFDM24_M 0x000000ff
190 #define R12A_TXAGC_OFDM24_S 0
191 #define R12A_TXAGC_OFDM36_M 0x0000ff00
193 #define R12A_TXAGC_OFDM48_M 0x00ff0000
195 #define R12A_TXAGC_OFDM54_M 0xff000000
199 #define R12A_TXAGC_MCS0_M 0x000000ff
200 #define R12A_TXAGC_MCS0_S 0
201 #define R12A_TXAGC_MCS1_M 0x0000ff00
203 #define R12A_TXAGC_MCS2_M 0x00ff0000
205 #define R12A_TXAGC_MCS3_M 0xff000000
209 #define R12A_TXAGC_MCS4_M 0x000000ff
210 #define R12A_TXAGC_MCS4_S 0
211 #define R12A_TXAGC_MCS5_M 0x0000ff00
213 #define R12A_TXAGC_MCS6_M 0x00ff0000
215 #define R12A_TXAGC_MCS7_M 0xff000000
219 #define R12A_TXAGC_MCS8_M 0x000000ff
220 #define R12A_TXAGC_MCS8_S 0
221 #define R12A_TXAGC_MCS9_M 0x0000ff00
223 #define R12A_TXAGC_MCS10_M 0x00ff0000
225 #define R12A_TXAGC_MCS11_M 0xff000000
229 #define R12A_TXAGC_MCS12_M 0x000000ff
230 #define R12A_TXAGC_MCS12_S 0
231 #define R12A_TXAGC_MCS13_M 0x0000ff00
233 #define R12A_TXAGC_MCS14_M 0x00ff0000
235 #define R12A_TXAGC_MCS15_M 0xff000000
239 #define R12A_TXAGC_NSS1_MCS0_M 0x000000ff
240 #define R12A_TXAGC_NSS1_MCS0_S 0
241 #define R12A_TXAGC_NSS1_MCS1_M 0x0000ff00
243 #define R12A_TXAGC_NSS1_MCS2_M 0x00ff0000
245 #define R12A_TXAGC_NSS1_MCS3_M 0xff000000
249 #define R12A_TXAGC_NSS1_MCS4_M 0x000000ff
250 #define R12A_TXAGC_NSS1_MCS4_S 0
251 #define R12A_TXAGC_NSS1_MCS5_M 0x0000ff00
253 #define R12A_TXAGC_NSS1_MCS6_M 0x00ff0000
255 #define R12A_TXAGC_NSS1_MCS7_M 0xff000000
259 #define R12A_TXAGC_NSS1_MCS8_M 0x000000ff
260 #define R12A_TXAGC_NSS1_MCS8_S 0
261 #define R12A_TXAGC_NSS1_MCS9_M 0x0000ff00
263 #define R12A_TXAGC_NSS2_MCS0_M 0x00ff0000
265 #define R12A_TXAGC_NSS2_MCS1_M 0xff000000
269 #define R12A_TXAGC_NSS2_MCS2_M 0x000000ff
270 #define R12A_TXAGC_NSS2_MCS2_S 0
271 #define R12A_TXAGC_NSS2_MCS3_M 0x0000ff00
273 #define R12A_TXAGC_NSS2_MCS4_M 0x00ff0000
275 #define R12A_TXAGC_NSS2_MCS5_M 0xff000000
279 #define R12A_TXAGC_NSS2_MCS6_M 0x000000ff
280 #define R12A_TXAGC_NSS2_MCS6_S 0
281 #define R12A_TXAGC_NSS2_MCS7_M 0x0000ff00
283 #define R12A_TXAGC_NSS2_MCS8_M 0x00ff0000
285 #define R12A_TXAGC_NSS2_MCS9_M 0xff000000
291 #define R12A_RF_LCK 0xb4
294 #define R12A_RF_LCK_MODE 0x4000