Lines Matching +full:power +full:-
1 /*-
64 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT])
67 /* Write per-MCS Tx power. */
69 SM(R12A_TXAGC_MCS0, power[RTWN_RIDX_HT_MCS(0)]) |
70 SM(R12A_TXAGC_MCS1, power[RTWN_RIDX_HT_MCS(1)]) |
71 SM(R12A_TXAGC_MCS2, power[RTWN_RIDX_HT_MCS(2)]) |
72 SM(R12A_TXAGC_MCS3, power[RTWN_RIDX_HT_MCS(3)]));
74 SM(R12A_TXAGC_MCS4, power[RTWN_RIDX_HT_MCS(4)]) |
75 SM(R12A_TXAGC_MCS5, power[RTWN_RIDX_HT_MCS(5)]) |
76 SM(R12A_TXAGC_MCS6, power[RTWN_RIDX_HT_MCS(6)]) |
77 SM(R12A_TXAGC_MCS7, power[RTWN_RIDX_HT_MCS(7)]));
78 if (sc->ntxchains >= 2) {
80 SM(R12A_TXAGC_MCS8, power[RTWN_RIDX_HT_MCS(8)]) |
81 SM(R12A_TXAGC_MCS9, power[RTWN_RIDX_HT_MCS(9)]) |
82 SM(R12A_TXAGC_MCS10, power[RTWN_RIDX_HT_MCS(10)]) |
83 SM(R12A_TXAGC_MCS11, power[RTWN_RIDX_HT_MCS(11)]));
85 SM(R12A_TXAGC_MCS12, power[RTWN_RIDX_HT_MCS(12)]) |
86 SM(R12A_TXAGC_MCS13, power[RTWN_RIDX_HT_MCS(13)]) |
87 SM(R12A_TXAGC_MCS14, power[RTWN_RIDX_HT_MCS(14)]) |
88 SM(R12A_TXAGC_MCS15, power[RTWN_RIDX_HT_MCS(15)]));
91 /* TODO: HT MCS 16 -> 31 */
96 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT])
101 SM(R12A_TXAGC_NSS1_MCS0, power[RTWN_RIDX_VHT_MCS(0, 0)]) |
102 SM(R12A_TXAGC_NSS1_MCS1, power[RTWN_RIDX_VHT_MCS(0, 1)]) |
103 SM(R12A_TXAGC_NSS1_MCS2, power[RTWN_RIDX_VHT_MCS(0, 2)]) |
104 SM(R12A_TXAGC_NSS1_MCS3, power[RTWN_RIDX_VHT_MCS(0, 3)]));
108 SM(R12A_TXAGC_NSS1_MCS4, power[RTWN_RIDX_VHT_MCS(0, 4)]) |
109 SM(R12A_TXAGC_NSS1_MCS5, power[RTWN_RIDX_VHT_MCS(0, 5)]) |
110 SM(R12A_TXAGC_NSS1_MCS6, power[RTWN_RIDX_VHT_MCS(0, 6)]) |
111 SM(R12A_TXAGC_NSS1_MCS7, power[RTWN_RIDX_VHT_MCS(0, 7)]));
114 if (sc->ntxchains == 1) {
116 SM(R12A_TXAGC_NSS1_MCS8, power[RTWN_RIDX_VHT_MCS(0, 8)]) |
117 SM(R12A_TXAGC_NSS1_MCS9, power[RTWN_RIDX_VHT_MCS(0, 9)]) |
122 SM(R12A_TXAGC_NSS1_MCS8, power[RTWN_RIDX_VHT_MCS(0, 8)]) |
123 SM(R12A_TXAGC_NSS1_MCS9, power[RTWN_RIDX_VHT_MCS(0, 9)]) |
124 SM(R12A_TXAGC_NSS2_MCS0, power[RTWN_RIDX_VHT_MCS(1, 0)]) |
125 SM(R12A_TXAGC_NSS2_MCS1, power[RTWN_RIDX_VHT_MCS(1, 1)]));
129 if (sc->ntxchains > 1) {
131 SM(R12A_TXAGC_NSS2_MCS2, power[RTWN_RIDX_VHT_MCS(1, 2)]) |
132 SM(R12A_TXAGC_NSS2_MCS3, power[RTWN_RIDX_VHT_MCS(1, 3)]) |
133 SM(R12A_TXAGC_NSS2_MCS4, power[RTWN_RIDX_VHT_MCS(1, 4)]) |
134 SM(R12A_TXAGC_NSS2_MCS5, power[RTWN_RIDX_VHT_MCS(1, 5)]));
138 if (sc->ntxchains > 1) {
140 SM(R12A_TXAGC_NSS2_MCS2, power[RTWN_RIDX_VHT_MCS(1, 6)]) |
141 SM(R12A_TXAGC_NSS2_MCS3, power[RTWN_RIDX_VHT_MCS(1, 7)]) |
142 SM(R12A_TXAGC_NSS2_MCS4, power[RTWN_RIDX_VHT_MCS(1, 8)]) |
143 SM(R12A_TXAGC_NSS2_MCS5, power[RTWN_RIDX_VHT_MCS(1, 9)]));
152 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT])
156 /* Write per-CCK rate Tx power. */
158 SM(R12A_TXAGC_CCK1, power[RTWN_RIDX_CCK1]) |
159 SM(R12A_TXAGC_CCK2, power[RTWN_RIDX_CCK2]) |
160 SM(R12A_TXAGC_CCK55, power[RTWN_RIDX_CCK55]) |
161 SM(R12A_TXAGC_CCK11, power[RTWN_RIDX_CCK11]));
167 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT])
170 /* Write per-OFDM rate Tx power. */
172 SM(R12A_TXAGC_OFDM06, power[RTWN_RIDX_OFDM6]) |
173 SM(R12A_TXAGC_OFDM09, power[RTWN_RIDX_OFDM9]) |
174 SM(R12A_TXAGC_OFDM12, power[RTWN_RIDX_OFDM12]) |
175 SM(R12A_TXAGC_OFDM18, power[RTWN_RIDX_OFDM18]));
177 SM(R12A_TXAGC_OFDM24, power[RTWN_RIDX_OFDM24]) |
178 SM(R12A_TXAGC_OFDM36, power[RTWN_RIDX_OFDM36]) |
179 SM(R12A_TXAGC_OFDM48, power[RTWN_RIDX_OFDM48]) |
180 SM(R12A_TXAGC_OFDM54, power[RTWN_RIDX_OFDM54]));
185 const struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT])
193 power_level = (int32_t) power[RTWN_RIDX_HT_MCS(7)];
196 power_level -= 10;
198 power_level -= 8;
200 power_level -= 6;
215 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT])
218 r12a_write_txpower_cck(sc, chain, c, power);
219 r12a_write_txpower_ofdm(sc, chain, c, power);
220 r12a_write_txpower_ht(sc, chain, c, power);
221 r12a_write_txpower_vht(sc, chain, c, power);
223 r12a_tx_power_training(sc, chain, c, power);
241 return (-1);
245 return (-1);
263 return (-1);
266 KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags));
267 return (-1);
275 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT])
277 struct r12a_softc *rs = sc->sc_priv;
282 if (group == -1) { /* shouldn't happen */
283 device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__);
287 max_mcs = RTWN_RIDX_HT_MCS(sc->ntxchains * 8 - 1);
288 max_vht_mcs = RTWN_RIDX_VHT_MCS(sc->ntxchains, 9) - 1;
295 power[ridx] = rs->cck_tx_pwr[chain][group];
297 power[ridx] = rs->ht40_tx_pwr_2g[chain][group];
300 power[ridx] += rs->ofdm_tx_pwr_diff_2g[chain][0];
302 for (i = 0; i < sc->ntxchains; i++) {
308 pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i];
311 pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i];
313 pwr_diff = rs->bw20_tx_pwr_diff_2g[chain][i];
317 power[ridx] += pwr_diff;
322 power[ridx] = rs->ht40_tx_pwr_5g[chain][group];
325 power[ridx] = rs->ht40_tx_pwr_5g[chain][group];
327 /* Add power for OFDM rates */
329 power[ridx] += rs->ofdm_tx_pwr_diff_5g[chain][0];
331 for (i = 0; i < sc->ntxchains; i++) {
337 pwr_diff = rs->bw80_tx_pwr_diff_5g[chain][i];
340 pwr_diff = rs->bw40_tx_pwr_diff_5g[chain][i];
342 pwr_diff = rs->bw20_tx_pwr_diff_5g[chain][i];
347 power[ridx] += pwr_diff;
353 power[ridx] += pwr_diff;
360 if (power[ridx] > R92C_MAX_TX_PWR)
361 power[ridx] = R92C_MAX_TX_PWR;
366 if (power[ridx] > R92C_MAX_TX_PWR)
367 power[ridx] = R92C_MAX_TX_PWR;
371 if (sc->sc_debug & RTWN_DEBUG_TXPWR) {
372 /* Dump per-rate Tx power values. */
373 printf("Tx power for chain %d:\n", chain);
375 printf("Rate %d = %u\n", ridx, power[ridx]);
384 uint8_t power[RTWN_RIDX_COUNT];
387 for (i = 0; i < sc->ntxchains; i++) {
388 memset(power, 0, sizeof(power));
389 /* Compute per-rate Tx power values. */
390 r12a_get_txpower(sc, i, c, power);
391 /* Write per-rate Tx power values to hardware. */
392 r12a_write_txpower(sc, i, c, power);
399 struct r12a_softc *rs = sc->sc_priv;
402 if (rs->chip & R12A_CHIP_C_CUT) {
443 struct ieee80211com *ic = &sc->sc_ic;
444 struct r12a_softc *rs = sc->sc_priv;
450 if ((sc->sc_flags & (RTWN_STARTED | RTWN_RUNNING)) !=
460 swing = rs->tx_bbswing_2g;
463 swing = rs->tx_bbswing_5g;
465 KASSERT(0, ("wrong channel flags %08X\n", c->ic_flags));
478 val = 0x16a; /* -3 dB */
481 val = 0x101; /* -6 dB */
484 val = 0xb6; /* -9 dB */
516 for (i = 0; i < sc->nrxchains; i++) {
528 /* RTL8812AU-specific */
539 if (c->ic_ieee > c->ic_vht_ch_freq1) {
540 if (c->ic_ieee - c->ic_vht_ch_freq1 == 2) {
548 if (c->ic_vht_ch_freq1 - c->ic_ieee == 2) {
568 /* ADC160 - Set bit 30 */
585 else if (sc->nrxchains == 2 && sc->ntxchains == 2)
620 else if (sc->nrxchains == 2 && sc->ntxchains == 2)
640 if (sc->nrxchains == 2 && sc->ntxchains == 2)
650 /* RTL8812AU-specific */
653 for (i = 0; i < sc->nrxchains; i++)
656 /* Set Tx power for this new channel. */
663 struct r12a_softc *rs = sc->sc_priv;
675 switch (rs->rfe_type) {
719 struct r12a_softc *rs = sc->sc_priv;
731 device_printf(sc->sc_dev,
746 switch (rs->rfe_type) {