72 	if ((txmode & 0x07) != 0) {  in r12a_lc_calib()
84 	rtwn_rf_setbits(sc, 0, R12A_RF_LCK, 0, R12A_RF_LCK_MODE);  in r12a_lc_calib()
87 	chnlbw = rtwn_rf_read(sc, 0, R92C_RF_CHNLBW);  in r12a_lc_calib()
88 	rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, chnlbw | R92C_RF_CHNLBW_LCSTART);  in r12a_lc_calib()
94 	rtwn_rf_setbits(sc, 0, R12A_RF_LCK, R12A_RF_LCK_MODE, 0);  in r12a_lc_calib()
97 	if ((txmode & 0x07) != 0) {  in r12a_lc_calib()
105 		rtwn_write_1(sc, R92C_TXPAUSE, 0);  in r12a_lc_calib()
109 	rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, chnlbw);  in r12a_lc_calib()
119 	if (sc->fwver == 0x19)  in r12a_iq_calib_fw_supported()
122 	return (0);  in r12a_iq_calib_fw_supported()
133 	rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0);  in r12a_save_bb_afe_vals()
135 	for (i = 0; i < size; i++)  in r12a_save_bb_afe_vals()
146 	rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0);  in r12a_restore_bb_afe_vals()
148 	for (i = 0; i < size; i++)  in r12a_restore_bb_afe_vals()
159 	rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0);  in r12a_save_rf_vals()
161 	for (c = 0; c < sc->nrxchains; c++)  in r12a_save_rf_vals()
162 		for (i = 0; i < size; i++)  in r12a_save_rf_vals()
173 	rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0);  in r12a_restore_rf_vals()
175 	for (c = 0; c < sc->nrxchains; c++)  in r12a_restore_rf_vals()
176 		for (i = 0; i < size; i++)  in r12a_restore_rf_vals()
192 	rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0);  in r12a_iq_config_mac()
196 	rtwn_setbits_1(sc, R92C_BCN_CTRL(0), R92C_BCN_CTRL_EN_BCN, 0);  in r12a_iq_config_mac()
197 	rtwn_setbits_1(sc, R92C_BCN_CTRL(1), R92C_BCN_CTRL_EN_BCN, 0);  in r12a_iq_config_mac()
199 	rtwn_write_1(sc, R12A_OFDMCCK_EN, 0);  in r12a_iq_config_mac()
201 	rtwn_bb_setbits(sc, R12A_CCA_ON_SEC, 0x03, 0x0c);  in r12a_iq_config_mac()
203 	rtwn_write_1(sc, R12A_CCK_RX_PATH + 3, 0x0f);  in r12a_iq_config_mac()
224 	rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0, 0x80000000);  in r12a_iq_calib_sw()
225 	rfe[0] = rtwn_bb_read(sc, R12A_RFE(0));  in r12a_iq_calib_sw()
245 	rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0, 0x80000000);  in r12a_iq_calib_sw()
247 	/* Chain 0. */  in r12a_iq_calib_sw()
248 	rtwn_bb_write(sc, R12A_SLEEP_NAV(0), 0);  in r12a_iq_calib_sw()
249 	rtwn_bb_write(sc, R12A_PMPD(0), 0);  in r12a_iq_calib_sw()
250 	rtwn_bb_write(sc, 0xc88, 0);  in r12a_iq_calib_sw()
251 	rtwn_bb_write(sc, 0xc8c, 0x3c000000);  in r12a_iq_calib_sw()
252 	rtwn_bb_setbits(sc, 0xc90, 0, 0x00000080);  in r12a_iq_calib_sw()
253 	rtwn_bb_setbits(sc, 0xcc4, 0, 0x20040000);  in r12a_iq_calib_sw()
254 	rtwn_bb_setbits(sc, 0xcc8, 0, 0x20000000);  in r12a_iq_calib_sw()
257 	rtwn_bb_write(sc, R12A_SLEEP_NAV(1), 0);  in r12a_iq_calib_sw()
258 	rtwn_bb_write(sc, R12A_PMPD(1), 0);  in r12a_iq_calib_sw()
259 	rtwn_bb_write(sc, 0xe88, 0);  in r12a_iq_calib_sw()
260 	rtwn_bb_write(sc, 0xe8c, 0x3c000000);  in r12a_iq_calib_sw()
261 	rtwn_bb_setbits(sc, 0xe90, 0, 0x00000080);  in r12a_iq_calib_sw()
262 	rtwn_bb_setbits(sc, 0xec4, 0, 0x20040000);  in r12a_iq_calib_sw()
263 	rtwn_bb_setbits(sc, 0xec8, 0, 0x20000000);  in r12a_iq_calib_sw()
265 	rtwn_bb_write(sc, R12A_RFE(0), rfe[0]);  in r12a_iq_calib_sw()