61 	if (cond[0] == 0)  in r92c_check_condition()
65 	    "%s: condition byte 0: %02X; chip %02X, board %02X\n",  in r92c_check_condition()
66 	    __func__, cond[0], rs->chip, rs->board_type);  in r92c_check_condition()
82 	for (i = 0; i < RTWN_MAX_CONDITIONS && cond[i] != 0; i++)  in r92c_check_condition()
86 	return (0);  in r92c_check_condition()
94 	/* Reserve pages [0; page_count]. */  in r92c_llt_init()
95 	for (i = 0; i < sc->page_count; i++) {  in r92c_llt_init()
96 		if ((error = r92c_llt_write(sc, i, i + 1)) != 0)  in r92c_llt_init()
99 	/* NB: 0xff indicates end-of-list. */  in r92c_llt_init()
100 	if ((error = r92c_llt_write(sc, i, 0xff)) != 0)  in r92c_llt_init()
107 		if ((error = r92c_llt_write(sc, i, i + 1)) != 0)  in r92c_llt_init()
119 	    SM(R92C_PBP_PSTX, R92C_PBP_128)) == 0);  in r92c_set_page_size()
129 	for (i = 0; i < sc->bb_size; i++) {  in r92c_init_bb_common()
139 		for (j = 0; j < bb_prog->count; j++) {  in r92c_init_bb_common()
141 			    "BB: reg 0x%03x, val 0x%08x\n",  in r92c_init_bb_common()
151 		rtwn_bb_setbits(sc, R92C_FPGA0_TXINFO, 0x03, 0x02);  in r92c_init_bb_common()
152 		rtwn_bb_setbits(sc, R92C_FPGA1_TXINFO, 0x300033, 0x200022);  in r92c_init_bb_common()
153 		rtwn_bb_setbits(sc, R92C_CCK0_AFESETTING, 0xff000000,  in r92c_init_bb_common()
154 		    0x45000000);  in r92c_init_bb_common()
155 		rtwn_bb_setbits(sc, R92C_OFDM0_TRXPATHENA, 0xff, 0x23);  in r92c_init_bb_common()
156 		rtwn_bb_setbits(sc, R92C_OFDM0_AGCPARAM1, 0x30, 0x10);  in r92c_init_bb_common()
158 		rtwn_bb_setbits(sc, 0xe74, 0x0c000000, 0x08000000);  in r92c_init_bb_common()
159 		rtwn_bb_setbits(sc, 0xe78, 0x0c000000, 0x08000000);  in r92c_init_bb_common()
160 		rtwn_bb_setbits(sc, 0xe7c, 0x0c000000, 0x08000000);  in r92c_init_bb_common()
161 		rtwn_bb_setbits(sc, 0xe80, 0x0c000000, 0x08000000);  in r92c_init_bb_common()
162 		rtwn_bb_setbits(sc, 0xe88, 0x0c000000, 0x08000000);  in r92c_init_bb_common()
166 	for (i = 0; i < sc->agc_size; i++) {  in r92c_init_bb_common()
176 		for (j = 0; j < agc_prog->count; j++) {  in r92c_init_bb_common()
178 			    "AGC: val 0x%08x\n", agc_prog->val[j]);  in r92c_init_bb_common()
186 	if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR)  in r92c_init_bb_common()
199 	for (i = 0; rf_prog[i].reg != NULL; i++) {  in r92c_init_rf_chain()
209 		for (j = 0; j < prog->count; j++) {  in r92c_init_rf_chain()
211 			    "RF: reg 0x%02x, val 0x%05x\n",  in r92c_init_rf_chain()
219 			if (prog->reg[j] > 0xf8) {  in r92c_init_rf_chain()
239 	for (chain = 0, i = 0; chain < sc->nrxchains; chain++, i++) {  in r92c_init_rf()
244 		type = (reg >> off) & 0x10;  in r92c_init_rf()
248 		    0, 0x100000);  in r92c_init_rf()
252 		    0, 0x10);  in r92c_init_rf()
256 		    R92C_HSSI_PARAM2_ADDR_LENGTH, 0);  in r92c_init_rf()
259 		    R92C_HSSI_PARAM2_DATA_LENGTH, 0);  in r92c_init_rf()
267 		    0x10 << off, type << off);  in r92c_init_rf()
276 		rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255);  in r92c_init_rf()
277 		rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00);  in r92c_init_rf()
281 	rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_CCK_EN);  in r92c_init_rf()
282 	rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_OFDM_EN);  in r92c_init_rf()
289 	rtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a);  in r92c_init_edca()
290 	rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a);  in r92c_init_edca()
291 	rtwn_write_2(sc, R92C_SIFS_CCK, 0x100a);  in r92c_init_edca()
292 	rtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a);  in r92c_init_edca()
294 	rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);  in r92c_init_edca()
295 	rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);  in r92c_init_edca()
296 	rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324);  in r92c_init_edca()
297 	rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226);  in r92c_init_edca()
305 	rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631);	/* MCS7~0 */  in r92c_init_ampdu()
306 	rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16);  in r92c_init_ampdu()
307 	rtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708);  in r92c_init_ampdu()
318 	rtwn_setbits_1(sc, R92C_LEDCFG2, 0, 0x80);  in r92c_init_antsel()
319 	rtwn_bb_setbits(sc, R92C_FPGA0_RFPARAM(0), 0, 0x2000);  in r92c_init_antsel()
320 	reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));  in r92c_init_antsel()
322 	rtwn_setbits_1(sc, R92C_LEDCFG2, 0x80, 0);  in r92c_init_antsel()
331 	for (i = 0; i < sc->nrxchains; i++) {  in r92c_pa_bias_init()
334 		r92c_rf_write(sc, i, R92C_RF_IPA, 0x0f406);  in r92c_pa_bias_init()
335 		r92c_rf_write(sc, i, R92C_RF_IPA, 0x4f406);  in r92c_pa_bias_init()
336 		r92c_rf_write(sc, i, R92C_RF_IPA, 0x8f406);  in r92c_pa_bias_init()
337 		r92c_rf_write(sc, i, R92C_RF_IPA, 0xcf406);  in r92c_pa_bias_init()
339 	if (!(rs->pa_setting & 0x10))  in r92c_pa_bias_init()
340 		rtwn_setbits_1(sc, 0x16, 0xf0, 0x90);  in r92c_pa_bias_init()