Lines Matching refs:rtwn_bb_write
78 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1f); in r92c_iq_calib_chain()
79 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x10008c1f); in r92c_iq_calib_chain()
80 rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82140102); in r92c_iq_calib_chain()
83 rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160202); in r92c_iq_calib_chain()
85 rtwn_bb_write(sc, R92C_TX_IQK_TONE(1), 0x10008c22); in r92c_iq_calib_chain()
86 rtwn_bb_write(sc, R92C_RX_IQK_TONE(1), 0x10008c22); in r92c_iq_calib_chain()
87 rtwn_bb_write(sc, R92C_TX_IQK_PI(1), 0x82140102); in r92c_iq_calib_chain()
88 rtwn_bb_write(sc, R92C_RX_IQK_PI(1), 0x28160202); in r92c_iq_calib_chain()
90 rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160502); in r92c_iq_calib_chain()
93 rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x001028d1); in r92c_iq_calib_chain()
95 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000); in r92c_iq_calib_chain()
96 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000); in r92c_iq_calib_chain()
100 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 2); in r92c_iq_calib_chain()
101 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0); in r92c_iq_calib_chain()
158 rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0); in r92c_iq_calib_run()
160 rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0); in r92c_iq_calib_run()
163 rtwn_bb_write(sc, reg_adda[i], 0x04db25a4); in r92c_iq_calib_run()
168 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), in r92c_iq_calib_run()
170 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), in r92c_iq_calib_run()
192 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600); in r92c_iq_calib_run()
193 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4); in r92c_iq_calib_run()
194 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000); in r92c_iq_calib_run()
200 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); in r92c_iq_calib_run()
201 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000); in r92c_iq_calib_run()
213 rtwn_bb_write(sc, R92C_CONFIG_ANT(0), 0x00080000); in r92c_iq_calib_run()
215 rtwn_bb_write(sc, R92C_CONFIG_ANT(1), 0x00080000); in r92c_iq_calib_run()
217 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); in r92c_iq_calib_run()
218 rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00); in r92c_iq_calib_run()
219 rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800); in r92c_iq_calib_run()
224 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0); in r92c_iq_calib_run()
225 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); in r92c_iq_calib_run()
226 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); in r92c_iq_calib_run()
230 rtwn_bb_write(sc, reg_adda[i], 0x0b1b25a4); in r92c_iq_calib_run()
266 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, vals->cck0_afesetting); in r92c_iq_calib_run()
267 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, vals->ofdm0_trxpathena); in r92c_iq_calib_run()
268 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0); in r92c_iq_calib_run()
269 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1); in r92c_iq_calib_run()
270 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar); in r92c_iq_calib_run()
271 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0); in r92c_iq_calib_run()
272 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1); in r92c_iq_calib_run()
273 rtwn_bb_write(sc, R92C_CONFIG_ANT(0), vals->config_ant0); in r92c_iq_calib_run()
274 rtwn_bb_write(sc, R92C_CONFIG_ANT(1), vals->config_ant1); in r92c_iq_calib_run()
276 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0); in r92c_iq_calib_run()
277 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3); in r92c_iq_calib_run()
279 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3); in r92c_iq_calib_run()
283 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1); in r92c_iq_calib_run()
284 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1); in r92c_iq_calib_run()
288 rtwn_bb_write(sc, reg_adda[i], vals->adda[i]); in r92c_iq_calib_run()
295 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x01008c00); in r92c_iq_calib_run()
296 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x01008c00); in r92c_iq_calib_run()