135     uint16_t rx[2][2], struct r92c_iq_cal_reg_vals *vals)  in r92c_iq_calib_run()  argument
149 			vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]);  in r92c_iq_calib_run()
151 		vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE);  in r92c_iq_calib_run()
152 		vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0));  in r92c_iq_calib_run()
153 		vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1));  in r92c_iq_calib_run()
154 		vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG);  in r92c_iq_calib_run()
175 		vals->cck0_afesetting = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);  in r92c_iq_calib_run()
176 		vals->ofdm0_trxpathena =  in r92c_iq_calib_run()
178 		vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);  in r92c_iq_calib_run()
179 		vals->fpga0_rfifacesw0 =  in r92c_iq_calib_run()
181 		vals->fpga0_rfifacesw1 =  in r92c_iq_calib_run()
183 		vals->fpga0_rfifaceoe0 =  in r92c_iq_calib_run()
185 		vals->fpga0_rfifaceoe1 =  in r92c_iq_calib_run()
187 		vals->config_ant0 = rtwn_bb_read(sc, R92C_CONFIG_ANT(0));  in r92c_iq_calib_run()
188 		vals->config_ant1 = rtwn_bb_read(sc, R92C_CONFIG_ANT(1));  in r92c_iq_calib_run()
207 	    vals->bcn_ctrl[0] & ~R92C_BCN_CTRL_EN_BCN);  in r92c_iq_calib_run()
209 	    vals->bcn_ctrl[1] & ~R92C_BCN_CTRL_EN_BCN);  in r92c_iq_calib_run()
211 	    vals->gpio_muxcfg & ~R92C_GPIO_MUXCFG_ENBT);  in r92c_iq_calib_run()
266 	rtwn_bb_write(sc, R92C_CCK0_AFESETTING, vals->cck0_afesetting);  in r92c_iq_calib_run()
267 	rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, vals->ofdm0_trxpathena);  in r92c_iq_calib_run()
268 	rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0);  in r92c_iq_calib_run()
269 	rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1);  in r92c_iq_calib_run()
270 	rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar);  in r92c_iq_calib_run()
271 	rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0);  in r92c_iq_calib_run()
272 	rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1);  in r92c_iq_calib_run()
273 	rtwn_bb_write(sc, R92C_CONFIG_ANT(0), vals->config_ant0);  in r92c_iq_calib_run()
274 	rtwn_bb_write(sc, R92C_CONFIG_ANT(1), vals->config_ant1);  in r92c_iq_calib_run()
288 			rtwn_bb_write(sc, reg_adda[i], vals->adda[i]);  in r92c_iq_calib_run()
290 		rtwn_write_1(sc, R92C_TXPAUSE, vals->txpause);  in r92c_iq_calib_run()
291 		rtwn_write_1(sc, R92C_BCN_CTRL(0), vals->bcn_ctrl[0]);  in r92c_iq_calib_run()
292 		rtwn_write_1(sc, R92C_BCN_CTRL(1), vals->bcn_ctrl[1]);  in r92c_iq_calib_run()
293 		rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg);  in r92c_iq_calib_run()
381 	struct r92c_iq_cal_reg_vals vals;  in r92c_iq_calib()  local
387 		r92c_iq_calib_run(sc, n, tx[n], rx[n], &vals);  in r92c_iq_calib()