3 /*-
56 	uint8_t		bcn_ctrl[2];
71 r92c_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2],  in r92c_iq_calib_chain()  argument
72     uint16_t rx[2])  in r92c_iq_calib_chain()  argument
82 		if (sc->ntxchains > 1) {  in r92c_iq_calib_chain()
100 		rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 2);  in r92c_iq_calib_chain()
134 r92c_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2],  in r92c_iq_calib_run()  argument
135     uint16_t rx[2][2], struct r92c_iq_cal_reg_vals *vals)  in r92c_iq_calib_run()  argument
149 			vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]);  in r92c_iq_calib_run()
151 		vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE);  in r92c_iq_calib_run()
152 		vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0));  in r92c_iq_calib_run()
153 		vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1));  in r92c_iq_calib_run()
154 		vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG);  in r92c_iq_calib_run()
157 	if (sc->ntxchains == 1) {  in r92c_iq_calib_run()
175 		vals->cck0_afesetting = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);  in r92c_iq_calib_run()
176 		vals->ofdm0_trxpathena =  in r92c_iq_calib_run()
178 		vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);  in r92c_iq_calib_run()
179 		vals->fpga0_rfifacesw0 =  in r92c_iq_calib_run()
181 		vals->fpga0_rfifacesw1 =  in r92c_iq_calib_run()
183 		vals->fpga0_rfifaceoe0 =  in r92c_iq_calib_run()
185 		vals->fpga0_rfifaceoe1 =  in r92c_iq_calib_run()
187 		vals->config_ant0 = rtwn_bb_read(sc, R92C_CONFIG_ANT(0));  in r92c_iq_calib_run()
188 		vals->config_ant1 = rtwn_bb_read(sc, R92C_CONFIG_ANT(1));  in r92c_iq_calib_run()
199 	if (sc->ntxchains > 1) {  in r92c_iq_calib_run()
207 	    vals->bcn_ctrl[0] & ~R92C_BCN_CTRL_EN_BCN);  in r92c_iq_calib_run()
209 	    vals->bcn_ctrl[1] & ~R92C_BCN_CTRL_EN_BCN);  in r92c_iq_calib_run()
211 	    vals->gpio_muxcfg & ~R92C_GPIO_MUXCFG_ENBT);  in r92c_iq_calib_run()
214 	if (sc->ntxchains > 1)  in r92c_iq_calib_run()
221 	for (chain = 0; chain < sc->ntxchains; chain++) {  in r92c_iq_calib_run()
234 		for (i = 0; i < 2; i++) {  in r92c_iq_calib_run()
266 	rtwn_bb_write(sc, R92C_CCK0_AFESETTING, vals->cck0_afesetting);  in r92c_iq_calib_run()
267 	rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, vals->ofdm0_trxpathena);  in r92c_iq_calib_run()
268 	rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0);  in r92c_iq_calib_run()
269 	rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1);  in r92c_iq_calib_run()
270 	rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar);  in r92c_iq_calib_run()
271 	rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0);  in r92c_iq_calib_run()
272 	rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1);  in r92c_iq_calib_run()
273 	rtwn_bb_write(sc, R92C_CONFIG_ANT(0), vals->config_ant0);  in r92c_iq_calib_run()
274 	rtwn_bb_write(sc, R92C_CONFIG_ANT(1), vals->config_ant1);  in r92c_iq_calib_run()
278 	if (sc->ntxchains > 1)  in r92c_iq_calib_run()
288 			rtwn_bb_write(sc, reg_adda[i], vals->adda[i]);  in r92c_iq_calib_run()
290 		rtwn_write_1(sc, R92C_TXPAUSE, vals->txpause);  in r92c_iq_calib_run()
291 		rtwn_write_1(sc, R92C_BCN_CTRL(0), vals->bcn_ctrl[0]);  in r92c_iq_calib_run()
292 		rtwn_write_1(sc, R92C_BCN_CTRL(1), vals->bcn_ctrl[1]);  in r92c_iq_calib_run()
293 		rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg);  in r92c_iq_calib_run()
302 r92c_iq_calib_compare_results(struct rtwn_softc *sc, uint16_t tx1[2][2],  in r92c_iq_calib_compare_results()  argument
303     uint16_t rx1[2][2], uint16_t tx2[2][2], uint16_t rx2[2][2])  in r92c_iq_calib_compare_results()  argument
305 	int chain, i, tx_ok[2], rx_ok[2];  in r92c_iq_calib_compare_results()
308 	for (chain = 0; chain < sc->ntxchains; chain++) {  in r92c_iq_calib_compare_results()
309 		for (i = 0; i < 2; i++)	{  in r92c_iq_calib_compare_results()
310 			if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff ||  in r92c_iq_calib_compare_results()
314 			tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <=  in r92c_iq_calib_compare_results()
317 			rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <=  in r92c_iq_calib_compare_results()
322 	if (sc->ntxchains > 1)  in r92c_iq_calib_compare_results()
330 r92c_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2],  in r92c_iq_calib_write_results()  argument
331     uint16_t rx[2], int chain)  in r92c_iq_calib_write_results()  argument
382 	uint16_t tx[RTWN_IQ_CAL_NRUN][2][2], rx[RTWN_IQ_CAL_NRUN][2][2];  in r92c_iq_calib()
393 		valid = r92c_iq_calib_compare_results(sc, tx[n - 1],  in r92c_iq_calib()
394 		    rx[n - 1], tx[n], rx[n]);  in r92c_iq_calib()
401 		if (sc->ntxchains > 1)  in r92c_iq_calib()
410 	uint32_t rf_ac[2];  in r92c_lc_calib()
420 		for (i = 0; i < sc->nrxchains; i++) {  in r92c_lc_calib()
441 		for (i = 0; i < sc->nrxchains; i++)  in r92c_lc_calib()