Lines Matching +full:tx1 +full:- +full:0
3 /*-
76 if (chain == 0) { /* IQ calibration for chain 0. */ in r92c_iq_calib_chain()
77 /* IQ calibration settings for chain 0. */ in r92c_iq_calib_chain()
78 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1f); in r92c_iq_calib_chain()
79 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x10008c1f); in r92c_iq_calib_chain()
80 rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82140102); in r92c_iq_calib_chain()
82 if (sc->ntxchains > 1) { in r92c_iq_calib_chain()
83 rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160202); in r92c_iq_calib_chain()
85 rtwn_bb_write(sc, R92C_TX_IQK_TONE(1), 0x10008c22); in r92c_iq_calib_chain()
86 rtwn_bb_write(sc, R92C_RX_IQK_TONE(1), 0x10008c22); in r92c_iq_calib_chain()
87 rtwn_bb_write(sc, R92C_TX_IQK_PI(1), 0x82140102); in r92c_iq_calib_chain()
88 rtwn_bb_write(sc, R92C_RX_IQK_PI(1), 0x28160202); in r92c_iq_calib_chain()
90 rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160502); in r92c_iq_calib_chain()
93 rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x001028d1); in r92c_iq_calib_chain()
95 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000); in r92c_iq_calib_chain()
96 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000); in r92c_iq_calib_chain()
101 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0); in r92c_iq_calib_chain()
108 status = rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(0)); in r92c_iq_calib_chain()
111 return (0); /* Tx failed. */ in r92c_iq_calib_chain()
113 tx[0] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_BEFORE(chain)), in r92c_iq_calib_chain()
117 if (tx[0] == 0x142 || tx[1] == 0x042) in r92c_iq_calib_chain()
118 return (0); /* Tx failed. */ in r92c_iq_calib_chain()
123 rx[0] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_BEFORE(chain)), in r92c_iq_calib_chain()
127 if (rx[0] == 0x132 || rx[1] == 0x036) in r92c_iq_calib_chain()
139 0x85c, 0xe6c, 0xe70, 0xe74, in r92c_iq_calib_run()
140 0xe78, 0xe7c, 0xe80, 0xe84, in r92c_iq_calib_run()
141 0xe88, 0xe8c, 0xed0, 0xed4, in r92c_iq_calib_run()
142 0xed8, 0xedc, 0xee0, 0xeec in r92c_iq_calib_run()
147 if (n == 0) { in r92c_iq_calib_run()
148 for (i = 0; i < nitems(reg_adda); i++) in r92c_iq_calib_run()
149 vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]); in r92c_iq_calib_run()
151 vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE); in r92c_iq_calib_run()
152 vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0)); in r92c_iq_calib_run()
153 vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1)); in r92c_iq_calib_run()
154 vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG); in r92c_iq_calib_run()
157 if (sc->ntxchains == 1) { in r92c_iq_calib_run()
158 rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0); in r92c_iq_calib_run()
160 rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0); in r92c_iq_calib_run()
162 for (i = 0; i < nitems(reg_adda); i++) in r92c_iq_calib_run()
163 rtwn_bb_write(sc, reg_adda[i], 0x04db25a4); in r92c_iq_calib_run()
166 hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0)); in r92c_iq_calib_run()
168 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), in r92c_iq_calib_run()
174 if (n == 0) { in r92c_iq_calib_run()
175 vals->cck0_afesetting = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); in r92c_iq_calib_run()
176 vals->ofdm0_trxpathena = in r92c_iq_calib_run()
178 vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); in r92c_iq_calib_run()
179 vals->fpga0_rfifacesw0 = in r92c_iq_calib_run()
180 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0)); in r92c_iq_calib_run()
181 vals->fpga0_rfifacesw1 = in r92c_iq_calib_run()
183 vals->fpga0_rfifaceoe0 = in r92c_iq_calib_run()
184 rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0)); in r92c_iq_calib_run()
185 vals->fpga0_rfifaceoe1 = in r92c_iq_calib_run()
187 vals->config_ant0 = rtwn_bb_read(sc, R92C_CONFIG_ANT(0)); in r92c_iq_calib_run()
188 vals->config_ant1 = rtwn_bb_read(sc, R92C_CONFIG_ANT(1)); in r92c_iq_calib_run()
191 rtwn_bb_setbits(sc, R92C_CCK0_AFESETTING, 0, 0x0f000000); in r92c_iq_calib_run()
192 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600); in r92c_iq_calib_run()
193 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4); in r92c_iq_calib_run()
194 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000); in r92c_iq_calib_run()
195 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(0), 0, 0x04000400); in r92c_iq_calib_run()
196 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(0), 0x400, 0); in r92c_iq_calib_run()
197 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(1), 0x400, 0); in r92c_iq_calib_run()
199 if (sc->ntxchains > 1) { in r92c_iq_calib_run()
200 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); in r92c_iq_calib_run()
201 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000); in r92c_iq_calib_run()
206 rtwn_write_1(sc, R92C_BCN_CTRL(0), in r92c_iq_calib_run()
207 vals->bcn_ctrl[0] & ~R92C_BCN_CTRL_EN_BCN); in r92c_iq_calib_run()
209 vals->bcn_ctrl[1] & ~R92C_BCN_CTRL_EN_BCN); in r92c_iq_calib_run()
211 vals->gpio_muxcfg & ~R92C_GPIO_MUXCFG_ENBT); in r92c_iq_calib_run()
213 rtwn_bb_write(sc, R92C_CONFIG_ANT(0), 0x00080000); in r92c_iq_calib_run()
214 if (sc->ntxchains > 1) in r92c_iq_calib_run()
215 rtwn_bb_write(sc, R92C_CONFIG_ANT(1), 0x00080000); in r92c_iq_calib_run()
217 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); in r92c_iq_calib_run()
218 rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00); in r92c_iq_calib_run()
219 rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800); in r92c_iq_calib_run()
221 for (chain = 0; chain < sc->ntxchains; chain++) { in r92c_iq_calib_run()
222 if (chain > 0) { in r92c_iq_calib_run()
223 /* Put chain 0 on standby. */ in r92c_iq_calib_run()
224 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0); in r92c_iq_calib_run()
225 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); in r92c_iq_calib_run()
226 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); in r92c_iq_calib_run()
229 for (i = 0; i < nitems(reg_adda); i++) in r92c_iq_calib_run()
230 rtwn_bb_write(sc, reg_adda[i], 0x0b1b25a4); in r92c_iq_calib_run()
234 for (i = 0; i < 2; i++) { in r92c_iq_calib_run()
239 if (ret == 0) { in r92c_iq_calib_run()
243 tx[chain][0] = 0xff; in r92c_iq_calib_run()
244 tx[chain][1] = 0xff; in r92c_iq_calib_run()
245 rx[chain][0] = 0xff; in r92c_iq_calib_run()
246 rx[chain][1] = 0xff; in r92c_iq_calib_run()
251 rx[chain][0] = 0xff; in r92c_iq_calib_run()
252 rx[chain][1] = 0xff; in r92c_iq_calib_run()
261 "%s: results for run %d chain %d: tx[0] 0x%x, " in r92c_iq_calib_run()
262 "tx[1] 0x%x, rx[0] 0x%x, rx[1] 0x%x\n", __func__, n, chain, in r92c_iq_calib_run()
263 tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1]); in r92c_iq_calib_run()
266 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, vals->cck0_afesetting); in r92c_iq_calib_run()
267 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, vals->ofdm0_trxpathena); in r92c_iq_calib_run()
268 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0); in r92c_iq_calib_run()
269 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1); in r92c_iq_calib_run()
270 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar); in r92c_iq_calib_run()
271 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0); in r92c_iq_calib_run()
272 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1); in r92c_iq_calib_run()
273 rtwn_bb_write(sc, R92C_CONFIG_ANT(0), vals->config_ant0); in r92c_iq_calib_run()
274 rtwn_bb_write(sc, R92C_CONFIG_ANT(1), vals->config_ant1); in r92c_iq_calib_run()
276 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0); in r92c_iq_calib_run()
277 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3); in r92c_iq_calib_run()
278 if (sc->ntxchains > 1) in r92c_iq_calib_run()
279 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3); in r92c_iq_calib_run()
281 if (n != 0) { in r92c_iq_calib_run()
283 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1); in r92c_iq_calib_run()
287 for (i = 0; i < nitems(reg_adda); i++) in r92c_iq_calib_run()
288 rtwn_bb_write(sc, reg_adda[i], vals->adda[i]); in r92c_iq_calib_run()
290 rtwn_write_1(sc, R92C_TXPAUSE, vals->txpause); in r92c_iq_calib_run()
291 rtwn_write_1(sc, R92C_BCN_CTRL(0), vals->bcn_ctrl[0]); in r92c_iq_calib_run()
292 rtwn_write_1(sc, R92C_BCN_CTRL(1), vals->bcn_ctrl[1]); in r92c_iq_calib_run()
293 rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg); in r92c_iq_calib_run()
295 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x01008c00); in r92c_iq_calib_run()
296 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x01008c00); in r92c_iq_calib_run()
302 r92c_iq_calib_compare_results(struct rtwn_softc *sc, uint16_t tx1[2][2], in r92c_iq_calib_compare_results()
307 tx_ok[0] = tx_ok[1] = rx_ok[0] = rx_ok[1] = 0; in r92c_iq_calib_compare_results()
308 for (chain = 0; chain < sc->ntxchains; chain++) { in r92c_iq_calib_compare_results()
309 for (i = 0; i < 2; i++) { in r92c_iq_calib_compare_results()
310 if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff || in r92c_iq_calib_compare_results()
311 rx1[chain][i] == 0xff || rx2[chain][i] == 0xff) in r92c_iq_calib_compare_results()
314 tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <= in r92c_iq_calib_compare_results()
317 rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <= in r92c_iq_calib_compare_results()
322 if (sc->ntxchains > 1) in r92c_iq_calib_compare_results()
323 return (tx_ok[0] && tx_ok[1] && rx_ok[0] && rx_ok[1]); in r92c_iq_calib_compare_results()
325 return (tx_ok[0] && rx_ok[0]); in r92c_iq_calib_compare_results()
336 if (tx[0] == 0xff || tx[1] == 0xff) in r92c_iq_calib_write_results()
340 val = ((reg >> 22) & 0x3ff); in r92c_iq_calib_write_results()
341 x = tx[0]; in r92c_iq_calib_write_results()
342 if (x & 0x00000200) in r92c_iq_calib_write_results()
343 x |= 0xfffffc00; in r92c_iq_calib_write_results()
344 reg = (((x * val) >> 8) & 0x3ff); in r92c_iq_calib_write_results()
345 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x3ff, reg); in r92c_iq_calib_write_results()
346 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x80000000, in r92c_iq_calib_write_results()
347 ((x * val) & 0x80) << 24); in r92c_iq_calib_write_results()
350 if (y & 0x00000200) in r92c_iq_calib_write_results()
351 y |= 0xfffffc00; in r92c_iq_calib_write_results()
353 rtwn_bb_setbits(sc, R92C_OFDM0_TXAFE(chain), 0xf0000000, in r92c_iq_calib_write_results()
354 (tx_c & 0x3c0) << 22); in r92c_iq_calib_write_results()
355 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x003f0000, in r92c_iq_calib_write_results()
356 (tx_c & 0x3f) << 16); in r92c_iq_calib_write_results()
357 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x20000000, in r92c_iq_calib_write_results()
358 ((y * val) & 0x80) << 22); in r92c_iq_calib_write_results()
360 if (rx[0] == 0xff || rx[1] == 0xff) in r92c_iq_calib_write_results()
363 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0x3ff, in r92c_iq_calib_write_results()
364 rx[0] & 0x3ff); in r92c_iq_calib_write_results()
365 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0xfc00, in r92c_iq_calib_write_results()
366 (rx[1] & 0x3f) << 10); in r92c_iq_calib_write_results()
368 if (chain == 0) { in r92c_iq_calib_write_results()
369 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQEXTANTA, 0xf0000000, in r92c_iq_calib_write_results()
370 (rx[1] & 0x3c0) << 22); in r92c_iq_calib_write_results()
372 rtwn_bb_setbits(sc, R92C_OFDM0_AGCRSSITABLE, 0xf000, in r92c_iq_calib_write_results()
373 (rx[1] & 0x3c0) << 6); in r92c_iq_calib_write_results()
385 valid = 0; in r92c_iq_calib()
386 for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) { in r92c_iq_calib()
389 if (n == 0) in r92c_iq_calib()
393 valid = r92c_iq_calib_compare_results(sc, tx[n - 1], in r92c_iq_calib()
394 rx[n - 1], tx[n], rx[n]); in r92c_iq_calib()
400 r92c_iq_calib_write_results(sc, tx[n][0], rx[n][0], 0); in r92c_iq_calib()
401 if (sc->ntxchains > 1) in r92c_iq_calib()
415 if ((txmode & 0x70) != 0) { in r92c_lc_calib()
417 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); in r92c_lc_calib()
420 for (i = 0; i < sc->nrxchains; i++) { in r92c_lc_calib()
431 rtwn_rf_setbits(sc, 0, R92C_RF_CHNLBW, 0, R92C_RF_CHNLBW_LCSTART); in r92c_lc_calib()
437 if ((txmode & 0x70) != 0) { in r92c_lc_calib()
441 for (i = 0; i < sc->nrxchains; i++) in r92c_lc_calib()
445 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); in r92c_lc_calib()
452 rtwn_rf_write(sc, 0, R92C_RF_T_METER, R92C_RF_T_METER_START); in r92c_temp_measure()
458 return (MS(rtwn_rf_read(sc, 0, R92C_RF_T_METER), in r92c_temp_read()