Lines Matching +full:tx +full:- +full:rx
3 /*-
71 r92c_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2], in r92c_iq_calib_chain()
72 uint16_t rx[2]) in r92c_iq_calib_chain()
82 if (sc->ntxchains > 1) { in r92c_iq_calib_chain()
111 return (0); /* Tx failed. */ in r92c_iq_calib_chain()
112 /* Read Tx IQ calibration results. */ in r92c_iq_calib_chain()
113 tx[0] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_BEFORE(chain)), in r92c_iq_calib_chain()
115 tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(chain)), in r92c_iq_calib_chain()
117 if (tx[0] == 0x142 || tx[1] == 0x042) in r92c_iq_calib_chain()
118 return (0); /* Tx failed. */ in r92c_iq_calib_chain()
121 return (1); /* Rx failed. */ in r92c_iq_calib_chain()
122 /* Read Rx IQ calibration results. */ in r92c_iq_calib_chain()
123 rx[0] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_BEFORE(chain)), in r92c_iq_calib_chain()
125 rx[1] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(chain)), in r92c_iq_calib_chain()
127 if (rx[0] == 0x132 || rx[1] == 0x036) in r92c_iq_calib_chain()
128 return (1); /* Rx failed. */ in r92c_iq_calib_chain()
130 return (3); /* Both Tx and Rx succeeded. */ in r92c_iq_calib_chain()
134 r92c_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2], in r92c_iq_calib_run()
135 uint16_t rx[2][2], struct r92c_iq_cal_reg_vals *vals) in r92c_iq_calib_run()
149 vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]); in r92c_iq_calib_run()
151 vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE); in r92c_iq_calib_run()
152 vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0)); in r92c_iq_calib_run()
153 vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1)); in r92c_iq_calib_run()
154 vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG); in r92c_iq_calib_run()
157 if (sc->ntxchains == 1) { in r92c_iq_calib_run()
175 vals->cck0_afesetting = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); in r92c_iq_calib_run()
176 vals->ofdm0_trxpathena = in r92c_iq_calib_run()
178 vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); in r92c_iq_calib_run()
179 vals->fpga0_rfifacesw0 = in r92c_iq_calib_run()
181 vals->fpga0_rfifacesw1 = in r92c_iq_calib_run()
183 vals->fpga0_rfifaceoe0 = in r92c_iq_calib_run()
185 vals->fpga0_rfifaceoe1 = in r92c_iq_calib_run()
187 vals->config_ant0 = rtwn_bb_read(sc, R92C_CONFIG_ANT(0)); in r92c_iq_calib_run()
188 vals->config_ant1 = rtwn_bb_read(sc, R92C_CONFIG_ANT(1)); in r92c_iq_calib_run()
199 if (sc->ntxchains > 1) { in r92c_iq_calib_run()
207 vals->bcn_ctrl[0] & ~R92C_BCN_CTRL_EN_BCN); in r92c_iq_calib_run()
209 vals->bcn_ctrl[1] & ~R92C_BCN_CTRL_EN_BCN); in r92c_iq_calib_run()
211 vals->gpio_muxcfg & ~R92C_GPIO_MUXCFG_ENBT); in r92c_iq_calib_run()
214 if (sc->ntxchains > 1) in r92c_iq_calib_run()
221 for (chain = 0; chain < sc->ntxchains; chain++) { in r92c_iq_calib_run()
238 tx[chain], rx[chain]); in r92c_iq_calib_run()
241 "%s: chain %d: Tx failed.\n", in r92c_iq_calib_run()
243 tx[chain][0] = 0xff; in r92c_iq_calib_run()
244 tx[chain][1] = 0xff; in r92c_iq_calib_run()
245 rx[chain][0] = 0xff; in r92c_iq_calib_run()
246 rx[chain][1] = 0xff; in r92c_iq_calib_run()
249 "%s: chain %d: Rx failed.\n", in r92c_iq_calib_run()
251 rx[chain][0] = 0xff; in r92c_iq_calib_run()
252 rx[chain][1] = 0xff; in r92c_iq_calib_run()
255 "%s: chain %d: Both Tx and Rx " in r92c_iq_calib_run()
261 "%s: results for run %d chain %d: tx[0] 0x%x, " in r92c_iq_calib_run()
262 "tx[1] 0x%x, rx[0] 0x%x, rx[1] 0x%x\n", __func__, n, chain, in r92c_iq_calib_run()
263 tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1]); in r92c_iq_calib_run()
266 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, vals->cck0_afesetting); in r92c_iq_calib_run()
267 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, vals->ofdm0_trxpathena); in r92c_iq_calib_run()
268 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0); in r92c_iq_calib_run()
269 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1); in r92c_iq_calib_run()
270 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar); in r92c_iq_calib_run()
271 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0); in r92c_iq_calib_run()
272 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1); in r92c_iq_calib_run()
273 rtwn_bb_write(sc, R92C_CONFIG_ANT(0), vals->config_ant0); in r92c_iq_calib_run()
274 rtwn_bb_write(sc, R92C_CONFIG_ANT(1), vals->config_ant1); in r92c_iq_calib_run()
278 if (sc->ntxchains > 1) in r92c_iq_calib_run()
288 rtwn_bb_write(sc, reg_adda[i], vals->adda[i]); in r92c_iq_calib_run()
290 rtwn_write_1(sc, R92C_TXPAUSE, vals->txpause); in r92c_iq_calib_run()
291 rtwn_write_1(sc, R92C_BCN_CTRL(0), vals->bcn_ctrl[0]); in r92c_iq_calib_run()
292 rtwn_write_1(sc, R92C_BCN_CTRL(1), vals->bcn_ctrl[1]); in r92c_iq_calib_run()
293 rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg); in r92c_iq_calib_run()
308 for (chain = 0; chain < sc->ntxchains; chain++) { in r92c_iq_calib_compare_results()
314 tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <= in r92c_iq_calib_compare_results()
317 rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <= in r92c_iq_calib_compare_results()
322 if (sc->ntxchains > 1) in r92c_iq_calib_compare_results()
330 r92c_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2], in r92c_iq_calib_write_results()
331 uint16_t rx[2], int chain) in r92c_iq_calib_write_results()
336 if (tx[0] == 0xff || tx[1] == 0xff) in r92c_iq_calib_write_results()
341 x = tx[0]; in r92c_iq_calib_write_results()
349 y = tx[1]; in r92c_iq_calib_write_results()
360 if (rx[0] == 0xff || rx[1] == 0xff) in r92c_iq_calib_write_results()
364 rx[0] & 0x3ff); in r92c_iq_calib_write_results()
366 (rx[1] & 0x3f) << 10); in r92c_iq_calib_write_results()
370 (rx[1] & 0x3c0) << 22); in r92c_iq_calib_write_results()
373 (rx[1] & 0x3c0) << 6); in r92c_iq_calib_write_results()
382 uint16_t tx[RTWN_IQ_CAL_NRUN][2][2], rx[RTWN_IQ_CAL_NRUN][2][2]; in r92c_iq_calib() local
387 r92c_iq_calib_run(sc, n, tx[n], rx[n], &vals); in r92c_iq_calib()
393 valid = r92c_iq_calib_compare_results(sc, tx[n - 1], in r92c_iq_calib()
394 rx[n - 1], tx[n], rx[n]); in r92c_iq_calib()
400 r92c_iq_calib_write_results(sc, tx[n][0], rx[n][0], 0); in r92c_iq_calib()
401 if (sc->ntxchains > 1) in r92c_iq_calib()
402 r92c_iq_calib_write_results(sc, tx[n][1], rx[n][1], 1); in r92c_iq_calib()
416 /* Disable all continuous Tx. */ in r92c_lc_calib()
420 for (i = 0; i < sc->nrxchains; i++) { in r92c_lc_calib()
427 /* Block all Tx queues. */ in r92c_lc_calib()
438 /* Restore Tx mode. */ in r92c_lc_calib()
441 for (i = 0; i < sc->nrxchains; i++) in r92c_lc_calib()
444 /* Unblock all Tx queues. */ in r92c_lc_calib()