Lines Matching +full:dma +full:- +full:window

3 /*-
64 #define R92C_IMR_ROK		0x00000001	/* receive DMA OK */
65 #define R92C_IMR_VODOK		0x00000002	/* AC_VO DMA OK */
66 #define R92C_IMR_VIDOK		0x00000004	/* AC_VI DMA OK */
67 #define R92C_IMR_BEDOK		0x00000008	/* AC_BE DMA OK */
68 #define R92C_IMR_BKDOK		0x00000010	/* AC_BK DMA OK */
70 #define R92C_IMR_MGNTDOK	0x00000040	/* management queue DMA OK */
72 #define R92C_IMR_HIGHDOK	0x00000100	/* high queue DMA OK */
73 #define R92C_IMR_BDOK		0x00000200	/* beacon queue DMA OK */
74 #define R92C_IMR_ATIMEND	0x00000400	/* ATIM window end interrupt */
77 #define R92C_IMR_BCNINT		0x00002000	/* beacon DMA interrupt 0 */
82 #define R92C_IMR_BCNDOK1	0x00040000	/* beacon queue DMA OK (1) */
83 #define R92C_IMR_BCNDOK2	0x00080000	/* beacon queue DMA OK (2) */
84 #define R92C_IMR_BCNDOK3	0x00100000	/* beacon queue DMA OK (3) */
85 #define R92C_IMR_BCNDOK4	0x00200000	/* beacon queue DMA OK (4) */
86 #define R92C_IMR_BCNDOK5	0x00400000	/* beacon queue DMA OK (5) */
87 #define R92C_IMR_BCNDOK6	0x00800000	/* beacon queue DMA OK (6) */
88 #define R92C_IMR_BCNDOK7	0x01000000	/* beacon queue DMA OK (7) */
89 #define R92C_IMR_BCNDOK8	0x02000000	/* beacon queue DMA OK (8) */
90 #define R92C_IMR_BCNDMAINT1	0x04000000	/* beacon DMA interrupt 1 */
91 #define R92C_IMR_BCNDMAINT2	0x08000000	/* beacon DMA interrupt 2 */
92 #define R92C_IMR_BCNDMAINT3	0x10000000	/* beacon DMA interrupt 3 */
93 #define R92C_IMR_BCNDMAINT4	0x20000000	/* beacon DMA interrupt 4 */
94 #define R92C_IMR_BCNDMAINT5	0x40000000	/* beacon DMA interrupt 5 */
95 #define R92C_IMR_BCNDMAINT6	0x80000000	/* beacon DMA interrupt 6 */