3 /*-
82 		if (sc->ntxchains > 1) {  in r92ce_iq_calib_chain()
110 	if (status & (1 << (28 + chain * 3)))  in r92ce_iq_calib_chain()
120 	if (status & (1 << (27 + chain * 3)))  in r92ce_iq_calib_chain()
130 	return (3);	/* Both Tx and Rx succeeded. */  in r92ce_iq_calib_chain()
149 			vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]);  in r92ce_iq_calib_run()
151 		vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE);  in r92ce_iq_calib_run()
152 		vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0));  in r92ce_iq_calib_run()
153 		vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1));  in r92ce_iq_calib_run()
154 		vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG);  in r92ce_iq_calib_run()
157 	if (sc->ntxchains == 1) {  in r92ce_iq_calib_run()
175 		vals->ofdm0_trxpathena =  in r92ce_iq_calib_run()
177 		vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);  in r92ce_iq_calib_run()
178 		vals->fpga0_rfifacesw1 =  in r92ce_iq_calib_run()
185 	if (sc->ntxchains > 1) {  in r92ce_iq_calib_run()
193 	    vals->bcn_ctrl[0] & ~R92C_BCN_CTRL_EN_BCN);  in r92ce_iq_calib_run()
195 	    vals->bcn_ctrl[1] & ~R92C_BCN_CTRL_EN_BCN);  in r92ce_iq_calib_run()
197 	    vals->gpio_muxcfg & ~R92C_GPIO_MUXCFG_ENBT);  in r92ce_iq_calib_run()
200 	if (sc->ntxchains > 1)  in r92ce_iq_calib_run()
209 	for (chain = 0; chain < sc->ntxchains; chain++) {  in r92ce_iq_calib_run()
241 			} else if (ret == 3) {  in r92ce_iq_calib_run()
255 	    vals->ofdm0_trxpathena);  in r92ce_iq_calib_run()
257 	    vals->fpga0_rfifacesw1);  in r92ce_iq_calib_run()
258 	rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar);  in r92ce_iq_calib_run()
262 	if (sc->ntxchains > 1)  in r92ce_iq_calib_run()
272 			rtwn_bb_write(sc, reg_adda[i], vals->adda[i]);  in r92ce_iq_calib_run()
274 		rtwn_write_1(sc, R92C_TXPAUSE, vals->txpause);  in r92ce_iq_calib_run()
275 		rtwn_write_1(sc, R92C_BCN_CTRL(0), vals->bcn_ctrl[0]);  in r92ce_iq_calib_run()
276 		rtwn_write_1(sc, R92C_BCN_CTRL(1), vals->bcn_ctrl[1]);  in r92ce_iq_calib_run()
277 		rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg);  in r92ce_iq_calib_run()
283 r92ce_iq_calib_compare_results(struct rtwn_softc *sc, uint16_t tx1[2][2],  in r92ce_iq_calib_compare_results()
289 	for (chain = 0; chain < sc->ntxchains; chain++) {  in r92ce_iq_calib_compare_results()
291 			if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff ||  in r92ce_iq_calib_compare_results()
295 			tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <=  in r92ce_iq_calib_compare_results()
298 			rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <=  in r92ce_iq_calib_compare_results()
303 	if (sc->ntxchains > 1)  in r92ce_iq_calib_compare_results()
358 #define RTWN_IQ_CAL_NRUN	3
374 		valid = r92ce_iq_calib_compare_results(sc, tx[n - 1],  in r92ce_iq_calib()
375 		    rx[n - 1], tx[n], rx[n]);  in r92ce_iq_calib()
382 		if (sc->ntxchains > 1)  in r92ce_iq_calib()