Lines Matching +full:dma +full:- +full:window

1 /*-
3  * Copyright (c) 2015-2016 Andriy Voskoboinyk <avos@FreeBSD.org>
47 #define R88E_HIMR_ROK		0x00000001	/* receive DMA OK */
49 #define R88E_HIMR_VODOK		0x00000004	/* AC_VO DMA OK */
50 #define R88E_HIMR_VIDOK		0x00000008	/* AC_VI DMA OK */
51 #define R88E_HIMR_BEDOK		0x00000010	/* AC_BE DMA OK */
52 #define R88E_HIMR_BKDOK		0x00000020	/* AC_BK DMA OK */
53 #define R88E_HIMR_MGNTDOK	0x00000040	/* management queue DMA OK */
54 #define R88E_HIMR_HIGHDOK	0x00000080	/* high queue DMA OK */
59 #define R88E_HIMR_ATIMEND	0x00001000	/* ATIM window end interrupt */
61 #define R88E_HIMR_BCNDERR	0x00010000	/* beacon queue DMA error */
62 #define R88E_HIMR_BCNINT	0x00100000	/* beacon DMA interrupt 0 */
76 #define R88E_HIMRE_BCNDOK1	0x00004000	/* beacon queue DMA OK (1) */
77 #define R88E_HIMRE_BCNDOK2	0x00008000	/* beacon queue DMA OK (2) */
78 #define R88E_HIMRE_BCNDOK3	0x00010000	/* beacon queue DMA OK (3) */
79 #define R88E_HIMRE_BCNDOK4	0x00020000	/* beacon queue DMA OK (4) */
80 #define R88E_HIMRE_BCNDOK5	0x00040000	/* beacon queue DMA OK (5) */
81 #define R88E_HIMRE_BCNDOK6	0x00080000	/* beacon queue DMA OK (6) */
82 #define R88E_HIMRE_BCNDOK7	0x00100000	/* beacon queue DMA OK (7) */
83 #define R88E_HIMRE_BCNDMAINT1	0x00200000	/* beacon DMA interrupt 1 */
84 #define R88E_HIMRE_BCNDMAINT2	0x00400000	/* beacon DMA interrupt 2 */
85 #define R88E_HIMRE_BCNDMAINT3	0x00800000	/* beacon DMA interrupt 3 */
86 #define R88E_HIMRE_BCNDMAINT4	0x01000000	/* beacon DMA interrupt 4 */
87 #define R88E_HIMRE_BCNDMAINT5	0x02000000	/* beacon DMA interrupt 5 */
88 #define R88E_HIMRE_BCNDMAINT6	0x04000000	/* beacon DMA interrupt 6 */
89 #define R88E_HIMRE_BCNDMAINT7	0x08000000	/* beacon DMA interrupt 7 */