1 /*-
2  * Copyright (c) 2016-2019 Andriy Voskoboinyk <avos@FreeBSD.org>
75 	rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(1), 0xf117b);  in r88e_iq_calib_chain()
100 	if (status & (1 << 28))  in r88e_iq_calib_chain()
106 	tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(0)),  in r88e_iq_calib_chain()
108 	if (tx[0] == 0x142 || tx[1] == 0x042)  in r88e_iq_calib_chain()
111 	rtwn_bb_write(sc, R92C_TX_IQK, 0x80007c00 | (tx[0] << 16) | tx[1]);  in r88e_iq_calib_chain()
118 	rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(1), 0xf7ffa);  in r88e_iq_calib_chain()
142 	if (status & (1 << 27))  in r88e_iq_calib_chain()
143 		return (1);	/* Rx failed. */  in r88e_iq_calib_chain()
148 	rx[1] = MS(status, R92C_POWER_IQK_RESULT);  in r88e_iq_calib_chain()
149 	if (rx[0] == 0x132 || rx[1] == 0x036)  in r88e_iq_calib_chain()
150 		return (1);	/* Rx failed. */  in r88e_iq_calib_chain()
171 			vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]);  in r88e_iq_calib_run()
173 		vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE);  in r88e_iq_calib_run()
174 		vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0));  in r88e_iq_calib_run()
175 		vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1));  in r88e_iq_calib_run()
176 		vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG);  in r88e_iq_calib_run()
180 	for (i = 1; i < nitems(reg_adda); i++)  in r88e_iq_calib_run()
187 		rtwn_bb_write(sc, R92C_HSSI_PARAM1(1),  in r88e_iq_calib_run()
192 		vals->cck0_afesetting = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);  in r88e_iq_calib_run()
193 		vals->ofdm0_trxpathena =  in r88e_iq_calib_run()
195 		vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);  in r88e_iq_calib_run()
196 		vals->fpga0_rfifacesw0 =  in r88e_iq_calib_run()
198 		vals->fpga0_rfifacesw1 =  in r88e_iq_calib_run()
199 		    rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));  in r88e_iq_calib_run()
200 		vals->fpga0_rfifaceoe0 =  in r88e_iq_calib_run()
202 		vals->fpga0_rfifaceoe1 =  in r88e_iq_calib_run()
203 		    rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(1));  in r88e_iq_calib_run()
204 		vals->config_ant0 = rtwn_bb_read(sc, R92C_CONFIG_ANT(0));  in r88e_iq_calib_run()
205 		vals->config_ant1 = rtwn_bb_read(sc, R92C_CONFIG_ANT(1));  in r88e_iq_calib_run()
211 	rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000);  in r88e_iq_calib_run()
214 	rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(1), 0x400, 0);  in r88e_iq_calib_run()
219 	    vals->bcn_ctrl[0] & ~R92C_BCN_CTRL_EN_BCN);  in r88e_iq_calib_run()
220 	rtwn_write_1(sc, R92C_BCN_CTRL(1),  in r88e_iq_calib_run()
221 	    vals->bcn_ctrl[1] & ~R92C_BCN_CTRL_EN_BCN);  in r88e_iq_calib_run()
223 	    vals->gpio_muxcfg & ~R92C_GPIO_MUXCFG_ENBT);  in r88e_iq_calib_run()
240 			tx[1] = 0xff;  in r88e_iq_calib_run()
242 			rx[1] = 0xff;  in r88e_iq_calib_run()
243 		} else if (ret == 1) {  in r88e_iq_calib_run()
247 			rx[1] = 0xff;  in r88e_iq_calib_run()
255 	    "%s: results for run %d: tx[0] 0x%x, tx[1] 0x%x, rx[0] 0x%x, "  in r88e_iq_calib_run()
256 	    "rx[1] 0x%x\n", __func__, n, tx[0], tx[1], rx[0], rx[1]);  in r88e_iq_calib_run()
258 	rtwn_bb_write(sc, R92C_CCK0_AFESETTING, vals->cck0_afesetting);  in r88e_iq_calib_run()
259 	rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, vals->ofdm0_trxpathena);  in r88e_iq_calib_run()
260 	rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0);  in r88e_iq_calib_run()
261 	rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1);  in r88e_iq_calib_run()
262 	rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar);  in r88e_iq_calib_run()
263 	rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0);  in r88e_iq_calib_run()
264 	rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1);  in r88e_iq_calib_run()
265 	rtwn_bb_write(sc, R92C_CONFIG_ANT(0), vals->config_ant0);  in r88e_iq_calib_run()
266 	rtwn_bb_write(sc, R92C_CONFIG_ANT(1), vals->config_ant1);  in r88e_iq_calib_run()
274 			rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1);  in r88e_iq_calib_run()
278 			rtwn_bb_write(sc, reg_adda[i], vals->adda[i]);  in r88e_iq_calib_run()
280 		rtwn_write_1(sc, R92C_TXPAUSE, vals->txpause);  in r88e_iq_calib_run()
281 		rtwn_write_1(sc, R92C_BCN_CTRL(0), vals->bcn_ctrl[0]);  in r88e_iq_calib_run()
282 		rtwn_write_1(sc, R92C_BCN_CTRL(1), vals->bcn_ctrl[1]);  in r88e_iq_calib_run()
283 		rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg);  in r88e_iq_calib_run()
289 r88e_iq_calib_compare_results(struct rtwn_softc *sc, uint16_t tx1[2],  in r88e_iq_calib_compare_results()
296 		if (tx1[i] == 0xff || tx2[i] == 0xff ||  in r88e_iq_calib_compare_results()
300 		tx_ok = (abs(tx1[i] - tx2[i]) <= RTWN_IQ_CAL_MAX_TOLERANCE);  in r88e_iq_calib_compare_results()
301 		rx_ok = (abs(rx1[i] - rx2[i]) <= RTWN_IQ_CAL_MAX_TOLERANCE);  in r88e_iq_calib_compare_results()
315 	if (tx[0] == 0xff || tx[1] == 0xff)  in r88e_iq_calib_write_results()
328 	y = tx[1];  in r88e_iq_calib_write_results()
339 	if (rx[0] == 0xff || rx[1] == 0xff)  in r88e_iq_calib_write_results()
345 	    (rx[1] & 0x3f) << 10);  in r88e_iq_calib_write_results()
347 	    (rx[1] & 0x3c0) << 22);  in r88e_iq_calib_write_results()
358 	KASSERT(sc->ntxchains == 1,  in r88e_iq_calib()
359 	    ("%s: only 1T1R configuration is supported!\n", __func__));  in r88e_iq_calib()
369 		valid = r88e_iq_calib_compare_results(sc, tx[n - 1],  in r88e_iq_calib()
370 		    rx[n - 1], tx[n], rx[n]);  in r88e_iq_calib()