Lines Matching +full:tx1 +full:- +full:0

1 /*-
2 * Copyright (c) 2016-2019 Andriy Voskoboinyk <avos@FreeBSD.org>
71 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0); in r88e_iq_calib_chain()
72 rtwn_rf_write(sc, 0, R88E_RF_WE_LUT, 0x800a0); in r88e_iq_calib_chain()
73 rtwn_rf_write(sc, 0, R92C_RF_RCK_OS, 0x30000); in r88e_iq_calib_chain()
74 rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(0), 0xf); in r88e_iq_calib_chain()
75 rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(1), 0xf117b); in r88e_iq_calib_chain()
76 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); in r88e_iq_calib_chain()
79 rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00); in r88e_iq_calib_chain()
80 rtwn_bb_write(sc, R92C_RX_IQK, 0x81004800); in r88e_iq_calib_chain()
82 /* IQ calibration settings for chain 0. */ in r88e_iq_calib_chain()
83 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1c); in r88e_iq_calib_chain()
84 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x30008c1c); in r88e_iq_calib_chain()
85 rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82160804); in r88e_iq_calib_chain()
86 rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160000); in r88e_iq_calib_chain()
89 rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x0046a911); in r88e_iq_calib_chain()
92 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000); in r88e_iq_calib_chain()
93 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000); in r88e_iq_calib_chain()
99 status = rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(0)); in r88e_iq_calib_chain()
101 return (0); /* Tx failed. */ in r88e_iq_calib_chain()
104 tx[0] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_BEFORE(0)), in r88e_iq_calib_chain()
106 tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(0)), in r88e_iq_calib_chain()
108 if (tx[0] == 0x142 || tx[1] == 0x042) in r88e_iq_calib_chain()
109 return (0); /* Tx failed. */ in r88e_iq_calib_chain()
111 rtwn_bb_write(sc, R92C_TX_IQK, 0x80007c00 | (tx[0] << 16) | tx[1]); in r88e_iq_calib_chain()
114 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0); in r88e_iq_calib_chain()
115 rtwn_rf_write(sc, 0, R88E_RF_WE_LUT, 0x800a0); in r88e_iq_calib_chain()
116 rtwn_rf_write(sc, 0, R92C_RF_RCK_OS, 0x30000); in r88e_iq_calib_chain()
117 rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(0), 0xf); in r88e_iq_calib_chain()
118 rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(1), 0xf7ffa); in r88e_iq_calib_chain()
119 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); in r88e_iq_calib_chain()
122 rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800); in r88e_iq_calib_chain()
124 /* IQ calibration settings for chain 0. */ in r88e_iq_calib_chain()
125 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x30008c1c); in r88e_iq_calib_chain()
126 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x10008c1c); in r88e_iq_calib_chain()
127 rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82160c05); in r88e_iq_calib_chain()
128 rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160c05); in r88e_iq_calib_chain()
131 rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x0046a911); in r88e_iq_calib_chain()
134 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000); in r88e_iq_calib_chain()
135 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000); in r88e_iq_calib_chain()
141 status = rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(0)); in r88e_iq_calib_chain()
146 rx[0] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_BEFORE(0)), in r88e_iq_calib_chain()
149 if (rx[0] == 0x132 || rx[1] == 0x036) in r88e_iq_calib_chain()
161 0x85c, 0xe6c, 0xe70, 0xe74, in r88e_iq_calib_run()
162 0xe78, 0xe7c, 0xe80, 0xe84, in r88e_iq_calib_run()
163 0xe88, 0xe8c, 0xed0, 0xed4, in r88e_iq_calib_run()
164 0xed8, 0xedc, 0xee0, 0xeec in r88e_iq_calib_run()
169 if (n == 0) { in r88e_iq_calib_run()
170 for (i = 0; i < nitems(reg_adda); i++) in r88e_iq_calib_run()
171 vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]); in r88e_iq_calib_run()
173 vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE); in r88e_iq_calib_run()
174 vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0)); in r88e_iq_calib_run()
175 vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1)); in r88e_iq_calib_run()
176 vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG); in r88e_iq_calib_run()
179 rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0); in r88e_iq_calib_run()
181 rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0); in r88e_iq_calib_run()
183 hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0)); in r88e_iq_calib_run()
185 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), in r88e_iq_calib_run()
191 if (n == 0) { in r88e_iq_calib_run()
192 vals->cck0_afesetting = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); in r88e_iq_calib_run()
193 vals->ofdm0_trxpathena = in r88e_iq_calib_run()
195 vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); in r88e_iq_calib_run()
196 vals->fpga0_rfifacesw0 = in r88e_iq_calib_run()
197 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0)); in r88e_iq_calib_run()
198 vals->fpga0_rfifacesw1 = in r88e_iq_calib_run()
200 vals->fpga0_rfifaceoe0 = in r88e_iq_calib_run()
201 rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0)); in r88e_iq_calib_run()
202 vals->fpga0_rfifaceoe1 = in r88e_iq_calib_run()
204 vals->config_ant0 = rtwn_bb_read(sc, R92C_CONFIG_ANT(0)); in r88e_iq_calib_run()
205 vals->config_ant1 = rtwn_bb_read(sc, R92C_CONFIG_ANT(1)); in r88e_iq_calib_run()
208 rtwn_bb_setbits(sc, R92C_CCK0_AFESETTING, 0, 0x0f000000); in r88e_iq_calib_run()
209 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600); in r88e_iq_calib_run()
210 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4); in r88e_iq_calib_run()
211 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000); in r88e_iq_calib_run()
212 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(0), 0, 0x04000400); in r88e_iq_calib_run()
213 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(0), 0x400, 0); in r88e_iq_calib_run()
214 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(1), 0x400, 0); in r88e_iq_calib_run()
218 rtwn_write_1(sc, R92C_BCN_CTRL(0), in r88e_iq_calib_run()
219 vals->bcn_ctrl[0] & ~R92C_BCN_CTRL_EN_BCN); in r88e_iq_calib_run()
221 vals->bcn_ctrl[1] & ~R92C_BCN_CTRL_EN_BCN); in r88e_iq_calib_run()
223 vals->gpio_muxcfg & ~R92C_GPIO_MUXCFG_ENBT); in r88e_iq_calib_run()
225 rtwn_bb_write(sc, R92C_CONFIG_ANT(0), 0x0f600000); in r88e_iq_calib_run()
227 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); in r88e_iq_calib_run()
228 rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00); in r88e_iq_calib_run()
229 rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800); in r88e_iq_calib_run()
232 for (i = 0; i < 2; i++) { in r88e_iq_calib_run()
236 if (ret == 0) { in r88e_iq_calib_run()
239 tx[0] = 0xff; in r88e_iq_calib_run()
240 tx[1] = 0xff; in r88e_iq_calib_run()
241 rx[0] = 0xff; in r88e_iq_calib_run()
242 rx[1] = 0xff; in r88e_iq_calib_run()
246 rx[0] = 0xff; in r88e_iq_calib_run()
247 rx[1] = 0xff; in r88e_iq_calib_run()
255 "%s: results for run %d: tx[0] 0x%x, tx[1] 0x%x, rx[0] 0x%x, " in r88e_iq_calib_run()
256 "rx[1] 0x%x\n", __func__, n, tx[0], tx[1], rx[0], rx[1]); in r88e_iq_calib_run()
258 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, vals->cck0_afesetting); in r88e_iq_calib_run()
259 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, vals->ofdm0_trxpathena); in r88e_iq_calib_run()
260 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0); in r88e_iq_calib_run()
261 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1); in r88e_iq_calib_run()
262 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar); in r88e_iq_calib_run()
263 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0); in r88e_iq_calib_run()
264 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1); in r88e_iq_calib_run()
265 rtwn_bb_write(sc, R92C_CONFIG_ANT(0), vals->config_ant0); in r88e_iq_calib_run()
266 rtwn_bb_write(sc, R92C_CONFIG_ANT(1), vals->config_ant1); in r88e_iq_calib_run()
268 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0); in r88e_iq_calib_run()
269 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3); in r88e_iq_calib_run()
271 if (n != 0) { in r88e_iq_calib_run()
273 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1); in r88e_iq_calib_run()
277 for (i = 0; i < nitems(reg_adda); i++) in r88e_iq_calib_run()
278 rtwn_bb_write(sc, reg_adda[i], vals->adda[i]); in r88e_iq_calib_run()
280 rtwn_write_1(sc, R92C_TXPAUSE, vals->txpause); in r88e_iq_calib_run()
281 rtwn_write_1(sc, R92C_BCN_CTRL(0), vals->bcn_ctrl[0]); in r88e_iq_calib_run()
282 rtwn_write_1(sc, R92C_BCN_CTRL(1), vals->bcn_ctrl[1]); in r88e_iq_calib_run()
283 rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg); in r88e_iq_calib_run()
289 r88e_iq_calib_compare_results(struct rtwn_softc *sc, uint16_t tx1[2], in r88e_iq_calib_compare_results()
294 tx_ok = rx_ok = 0; in r88e_iq_calib_compare_results()
295 for (i = 0; i < 2; i++) { in r88e_iq_calib_compare_results()
296 if (tx1[i] == 0xff || tx2[i] == 0xff || in r88e_iq_calib_compare_results()
297 rx1[i] == 0xff || rx2[i] == 0xff) in r88e_iq_calib_compare_results()
300 tx_ok = (abs(tx1[i] - tx2[i]) <= RTWN_IQ_CAL_MAX_TOLERANCE); in r88e_iq_calib_compare_results()
301 rx_ok = (abs(rx1[i] - rx2[i]) <= RTWN_IQ_CAL_MAX_TOLERANCE); in r88e_iq_calib_compare_results()
315 if (tx[0] == 0xff || tx[1] == 0xff) in r88e_iq_calib_write_results()
318 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(0)); in r88e_iq_calib_write_results()
319 val = ((reg >> 22) & 0x3ff); in r88e_iq_calib_write_results()
320 x = tx[0]; in r88e_iq_calib_write_results()
321 if (x & 0x00000200) in r88e_iq_calib_write_results()
322 x |= 0xfffffc00; in r88e_iq_calib_write_results()
323 reg = (((x * val) >> 8) & 0x3ff); in r88e_iq_calib_write_results()
324 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(0), 0x3ff, reg); in r88e_iq_calib_write_results()
325 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x80000000, in r88e_iq_calib_write_results()
326 ((x * val) & 0x80) << 24); in r88e_iq_calib_write_results()
329 if (y & 0x00000200) in r88e_iq_calib_write_results()
330 y |= 0xfffffc00; in r88e_iq_calib_write_results()
332 rtwn_bb_setbits(sc, R92C_OFDM0_TXAFE(0), 0xf0000000, in r88e_iq_calib_write_results()
333 (tx_c & 0x3c0) << 22); in r88e_iq_calib_write_results()
334 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(0), 0x003f0000, in r88e_iq_calib_write_results()
335 (tx_c & 0x3f) << 16); in r88e_iq_calib_write_results()
336 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x20000000, in r88e_iq_calib_write_results()
337 ((y * val) & 0x80) << 22); in r88e_iq_calib_write_results()
339 if (rx[0] == 0xff || rx[1] == 0xff) in r88e_iq_calib_write_results()
342 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(0), 0x3ff, in r88e_iq_calib_write_results()
343 rx[0] & 0x3ff); in r88e_iq_calib_write_results()
344 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(0), 0xfc00, in r88e_iq_calib_write_results()
345 (rx[1] & 0x3f) << 10); in r88e_iq_calib_write_results()
346 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQEXTANTA, 0xf0000000, in r88e_iq_calib_write_results()
347 (rx[1] & 0x3c0) << 22); in r88e_iq_calib_write_results()
358 KASSERT(sc->ntxchains == 1, in r88e_iq_calib()
361 valid = 0; in r88e_iq_calib()
362 for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) { in r88e_iq_calib()
365 if (n == 0) in r88e_iq_calib()
369 valid = r88e_iq_calib_compare_results(sc, tx[n - 1], in r88e_iq_calib()
370 rx[n - 1], tx[n], rx[n]); in r88e_iq_calib()
383 rtwn_rf_write(sc, 0, R88E_RF_T_METER, R88E_RF_T_METER_START); in r88e_temp_measure()
389 return (MS(rtwn_rf_read(sc, 0, R88E_RF_T_METER), in r88e_temp_read()