Lines Matching refs:sc
88 void (*rtsx_intr_trans_ok)(struct rtsx_softc *sc);
90 void (*rtsx_intr_trans_ko)(struct rtsx_softc *sc);
201 static int rtsx_dma_alloc(struct rtsx_softc *sc);
203 static void rtsx_dma_free(struct rtsx_softc *sc);
205 static void rtsx_handle_card_present(struct rtsx_softc *sc);
207 static bool rtsx_is_card_present(struct rtsx_softc *sc);
208 static int rtsx_init(struct rtsx_softc *sc);
210 static int rtsx_rts5227_fill_driving(struct rtsx_softc *sc);
211 static int rtsx_rts5249_fill_driving(struct rtsx_softc *sc);
212 static int rtsx_rts5260_fill_driving(struct rtsx_softc *sc);
214 static int rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val);
215 static int rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val);
216 static int rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val);
217 static int rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val);
218 static int rtsx_bus_power_off(struct rtsx_softc *sc);
219 static int rtsx_bus_power_on(struct rtsx_softc *sc);
220 static int rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width);
221 static int rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing);
222 static int rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq);
223 static int rtsx_stop_sd_clock(struct rtsx_softc *sc);
224 static int rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t…
226 static void rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point);
227 static void rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point);
228 static void rtsx_sd_tuning_rx_phase(struct rtsx_softc *sc, uint32_t *phase_map);
229 static int rtsx_sd_tuning_rx_cmd(struct rtsx_softc *sc, uint8_t sample_point);
230 static int rtsx_sd_tuning_rx_cmd_wait(struct rtsx_softc *sc, struct mmc_command *cmd);
231 static void rtsx_sd_tuning_rx_cmd_wakeup(struct rtsx_softc *sc);
232 static void rtsx_sd_wait_data_idle(struct rtsx_softc *sc);
233 static uint8_t rtsx_sd_search_final_rx_phase(struct rtsx_softc *sc, uint32_t phase_map);
237 static int rtsx_led_enable(struct rtsx_softc *sc);
238 static int rtsx_led_disable(struct rtsx_softc *sc);
241 static void rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd);
242 static void rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg,
244 static void rtsx_set_cmd_data_len(struct rtsx_softc *sc, uint16_t block_cnt, uint16_t byte_cnt);
245 static void rtsx_send_cmd(struct rtsx_softc *sc);
246 static void rtsx_ret_resp(struct rtsx_softc *sc);
247 static void rtsx_set_resp(struct rtsx_softc *sc, struct mmc_command *cmd);
248 static void rtsx_stop_cmd(struct rtsx_softc *sc);
249 static void rtsx_clear_error(struct rtsx_softc *sc);
250 static void rtsx_req_done(struct rtsx_softc *sc);
251 static int rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd);
252 static int rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd);
253 static void rtsx_ask_ppbuf_part1(struct rtsx_softc *sc);
254 static void rtsx_get_ppbuf_part1(struct rtsx_softc *sc);
255 static void rtsx_get_ppbuf_part2(struct rtsx_softc *sc);
256 static void rtsx_put_ppbuf_part1(struct rtsx_softc *sc);
257 static void rtsx_put_ppbuf_part2(struct rtsx_softc *sc);
258 static void rtsx_write_ppbuf(struct rtsx_softc *sc);
259 static int rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd);
260 static void rtsx_xfer_begin(struct rtsx_softc *sc);
261 static void rtsx_xfer_start(struct rtsx_softc *sc);
262 static void rtsx_xfer_finish(struct rtsx_softc *sc);
293 device_get_nameunit(sc->rtsx_dev), "rtsx", MTX_DEF)
318 #define READ4(sc, reg) \ argument
319 (bus_space_read_4((sc)->rtsx_mem_btag, (sc)->rtsx_mem_bhandle, (reg)))
320 #define WRITE4(sc, reg, val) \ argument
321 (bus_space_write_4((sc)->rtsx_mem_btag, (sc)->rtsx_mem_bhandle, (reg), (val)))
323 #define RTSX_READ(sc, reg, val) \ argument
325 int err = rtsx_read((sc), (reg), (val)); \
330 #define RTSX_WRITE(sc, reg, val) \ argument
332 int err = rtsx_write((sc), (reg), 0xff, (val)); \
336 #define RTSX_CLR(sc, reg, bits) \ argument
338 int err = rtsx_write((sc), (reg), (bits), 0); \
343 #define RTSX_SET(sc, reg, bits) \ argument
345 int err = rtsx_write((sc), (reg), (bits), 0xff);\
350 #define RTSX_BITOP(sc, reg, mask, bits) \ argument
352 int err = rtsx_write((sc), (reg), (mask), (bits)); \
407 rtsx_dma_alloc(struct rtsx_softc *sc) in rtsx_dma_alloc() argument
411 error = bus_dma_tag_create(bus_get_dma_tag(sc->rtsx_dev), /* inherit from parent */ in rtsx_dma_alloc()
420 &sc->rtsx_cmd_dma_tag); in rtsx_dma_alloc()
422 device_printf(sc->rtsx_dev, in rtsx_dma_alloc()
426 error = bus_dmamem_alloc(sc->rtsx_cmd_dma_tag, /* DMA tag */ in rtsx_dma_alloc()
427 &sc->rtsx_cmd_dmamem, /* will hold the KVA pointer */ in rtsx_dma_alloc()
429 &sc->rtsx_cmd_dmamap); /* DMA map */ in rtsx_dma_alloc()
431 device_printf(sc->rtsx_dev, in rtsx_dma_alloc()
436 error = bus_dmamap_load(sc->rtsx_cmd_dma_tag, /* DMA tag */ in rtsx_dma_alloc()
437 sc->rtsx_cmd_dmamap, /* DMA map */ in rtsx_dma_alloc()
438 sc->rtsx_cmd_dmamem, /* KVA pointer to be mapped */ in rtsx_dma_alloc()
441 &sc->rtsx_cmd_buffer, /* first arg of callback */ in rtsx_dma_alloc()
443 if (error || sc->rtsx_cmd_buffer == 0) { in rtsx_dma_alloc()
444 device_printf(sc->rtsx_dev, in rtsx_dma_alloc()
450 error = bus_dma_tag_create(bus_get_dma_tag(sc->rtsx_dev), /* inherit from parent */ in rtsx_dma_alloc()
459 &sc->rtsx_data_dma_tag); in rtsx_dma_alloc()
461 device_printf(sc->rtsx_dev, in rtsx_dma_alloc()
465 error = bus_dmamem_alloc(sc->rtsx_data_dma_tag, /* DMA tag */ in rtsx_dma_alloc()
466 &sc->rtsx_data_dmamem, /* will hold the KVA pointer */ in rtsx_dma_alloc()
468 &sc->rtsx_data_dmamap); /* DMA map */ in rtsx_dma_alloc()
470 device_printf(sc->rtsx_dev, in rtsx_dma_alloc()
474 error = bus_dmamap_load(sc->rtsx_data_dma_tag, /* DMA tag */ in rtsx_dma_alloc()
475 sc->rtsx_data_dmamap, /* DMA map */ in rtsx_dma_alloc()
476 sc->rtsx_data_dmamem, /* KVA pointer to be mapped */ in rtsx_dma_alloc()
479 &sc->rtsx_data_buffer, /* first arg of callback */ in rtsx_dma_alloc()
481 if (error || sc->rtsx_data_buffer == 0) { in rtsx_dma_alloc()
482 device_printf(sc->rtsx_dev, in rtsx_dma_alloc()
490 bus_dmamem_free(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamem, sc->rtsx_data_dmamap); in rtsx_dma_alloc()
492 bus_dma_tag_destroy(sc->rtsx_data_dma_tag); in rtsx_dma_alloc()
494 bus_dmamap_unload(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap); in rtsx_dma_alloc()
496 bus_dmamem_free(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamem, sc->rtsx_cmd_dmamap); in rtsx_dma_alloc()
498 bus_dma_tag_destroy(sc->rtsx_cmd_dma_tag); in rtsx_dma_alloc()
514 rtsx_dma_free(struct rtsx_softc *sc) in rtsx_dma_free() argument
516 if (sc->rtsx_cmd_dma_tag != NULL) { in rtsx_dma_free()
517 if (sc->rtsx_cmd_dmamap != NULL) in rtsx_dma_free()
518 bus_dmamap_unload(sc->rtsx_cmd_dma_tag, in rtsx_dma_free()
519 sc->rtsx_cmd_dmamap); in rtsx_dma_free()
520 if (sc->rtsx_cmd_dmamem != NULL) in rtsx_dma_free()
521 bus_dmamem_free(sc->rtsx_cmd_dma_tag, in rtsx_dma_free()
522 sc->rtsx_cmd_dmamem, in rtsx_dma_free()
523 sc->rtsx_cmd_dmamap); in rtsx_dma_free()
524 sc->rtsx_cmd_dmamap = NULL; in rtsx_dma_free()
525 sc->rtsx_cmd_dmamem = NULL; in rtsx_dma_free()
526 sc->rtsx_cmd_buffer = 0; in rtsx_dma_free()
527 bus_dma_tag_destroy(sc->rtsx_cmd_dma_tag); in rtsx_dma_free()
528 sc->rtsx_cmd_dma_tag = NULL; in rtsx_dma_free()
530 if (sc->rtsx_data_dma_tag != NULL) { in rtsx_dma_free()
531 if (sc->rtsx_data_dmamap != NULL) in rtsx_dma_free()
532 bus_dmamap_unload(sc->rtsx_data_dma_tag, in rtsx_dma_free()
533 sc->rtsx_data_dmamap); in rtsx_dma_free()
534 if (sc->rtsx_data_dmamem != NULL) in rtsx_dma_free()
535 bus_dmamem_free(sc->rtsx_data_dma_tag, in rtsx_dma_free()
536 sc->rtsx_data_dmamem, in rtsx_dma_free()
537 sc->rtsx_data_dmamap); in rtsx_dma_free()
538 sc->rtsx_data_dmamap = NULL; in rtsx_dma_free()
539 sc->rtsx_data_dmamem = NULL; in rtsx_dma_free()
540 sc->rtsx_data_buffer = 0; in rtsx_dma_free()
541 bus_dma_tag_destroy(sc->rtsx_data_dma_tag); in rtsx_dma_free()
542 sc->rtsx_data_dma_tag = NULL; in rtsx_dma_free()
549 struct rtsx_softc *sc = arg; in rtsx_intr() local
553 RTSX_LOCK(sc); in rtsx_intr()
555 enabled = sc->rtsx_intr_enabled; in rtsx_intr()
556 status = READ4(sc, RTSX_BIPR); /* read Bus Interrupt Pending Register */ in rtsx_intr()
557 sc->rtsx_intr_status = status; in rtsx_intr()
559 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) in rtsx_intr()
560 …device_printf(sc->rtsx_dev, "Interrupt handler - enabled: 0x%08x, status: 0x%08x\n", enabled, stat… in rtsx_intr()
563 WRITE4(sc, RTSX_BIPR, status); in rtsx_intr()
566 …device_printf(sc->rtsx_dev, "Spurious interrupt - enabled: 0x%08x, status: 0x%08x\n", enabled, sta… in rtsx_intr()
567 RTSX_UNLOCK(sc); in rtsx_intr()
573 sc->rtsx_read_only = 1; in rtsx_intr()
575 sc->rtsx_read_only = 0; in rtsx_intr()
579 device_printf(sc->rtsx_dev, "Interrupt card inserted/removed\n"); in rtsx_intr()
580 rtsx_handle_card_present(sc); in rtsx_intr()
583 if (sc->rtsx_req == NULL) { in rtsx_intr()
584 RTSX_UNLOCK(sc); in rtsx_intr()
589 sc->rtsx_req->cmd->error = MMC_ERR_NONE; in rtsx_intr()
590 if (sc->rtsx_intr_trans_ok != NULL) in rtsx_intr()
591 sc->rtsx_intr_trans_ok(sc); in rtsx_intr()
594 sc->rtsx_req->cmd->error = MMC_ERR_FAILED; in rtsx_intr()
595 if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 && in rtsx_intr()
597 device_printf(sc->rtsx_dev, "CRC error\n"); in rtsx_intr()
598 sc->rtsx_req->cmd->error = MMC_ERR_BADCRC; in rtsx_intr()
600 if (!sc->rtsx_tuning_mode) in rtsx_intr()
601 device_printf(sc->rtsx_dev, "Transfer fail - status: 0x%08x\n", status); in rtsx_intr()
602 rtsx_stop_cmd(sc); in rtsx_intr()
603 if (sc->rtsx_intr_trans_ko != NULL) in rtsx_intr()
604 sc->rtsx_intr_trans_ko(sc); in rtsx_intr()
607 RTSX_UNLOCK(sc); in rtsx_intr()
614 rtsx_handle_card_present(struct rtsx_softc *sc) in rtsx_handle_card_present() argument
620 was_present = sc->rtsx_cam_status; in rtsx_handle_card_present()
622 was_present = sc->rtsx_mmc_dev != NULL; in rtsx_handle_card_present()
624 is_present = rtsx_is_card_present(sc); in rtsx_handle_card_present()
626 device_printf(sc->rtsx_dev, "Card present\n"); in rtsx_handle_card_present()
628 device_printf(sc->rtsx_dev, "Card absent\n"); in rtsx_handle_card_present()
637 &sc->rtsx_card_insert_task, -hz); in rtsx_handle_card_present()
639 taskqueue_enqueue(taskqueue_bus, &sc->rtsx_card_remove_task); in rtsx_handle_card_present()
649 struct rtsx_softc *sc = arg; local
654 if (rtsx_is_card_present(sc)) {
655 sc->rtsx_flags |= RTSX_F_CARD_PRESENT;
658 if (sc->rtsx_cam_status == 0) {
660 if (sc->rtsx_mmc_dev == NULL) {
662 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
663 device_printf(sc->rtsx_dev, "Card inserted\n");
665 sc->rtsx_read_count = sc->rtsx_write_count = 0;
667 sc->rtsx_cam_status = 1;
668 mmc_cam_sim_discover(&sc->rtsx_mmc_sim);
670 sc->rtsx_mmc_dev = device_add_child(sc->rtsx_dev, "mmc", DEVICE_UNIT_ANY);
671 if (sc->rtsx_mmc_dev == NULL) {
672 device_printf(sc->rtsx_dev, "Adding MMC bus failed\n");
674 device_set_ivars(sc->rtsx_mmc_dev, sc);
675 device_probe_and_attach(sc->rtsx_mmc_dev);
680 sc->rtsx_flags &= ~RTSX_F_CARD_PRESENT;
683 if (sc->rtsx_cam_status != 0) {
685 if (sc->rtsx_mmc_dev != NULL) {
687 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
688 device_printf(sc->rtsx_dev, "Card removed\n");
690 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
691 device_printf(sc->rtsx_dev, "Read count: %" PRIu64 ", write count: %" PRIu64 "\n",
692 sc->rtsx_read_count, sc->rtsx_write_count);
694 sc->rtsx_cam_status = 0;
695 mmc_cam_sim_discover(&sc->rtsx_mmc_sim);
697 if (device_delete_child(sc->rtsx_dev, sc->rtsx_mmc_dev))
698 device_printf(sc->rtsx_dev, "Detaching MMC bus failed\n");
699 sc->rtsx_mmc_dev = NULL;
709 rtsx_is_card_present(struct rtsx_softc *sc) argument
713 status = READ4(sc, RTSX_BIPR);
714 if (sc->rtsx_inversion == 0)
721 rtsx_init(struct rtsx_softc *sc) argument
727 sc->rtsx_host.host_ocr = RTSX_SUPPORTED_VOLTAGE;
728 sc->rtsx_host.f_min = RTSX_SDCLK_250KHZ;
729 sc->rtsx_host.f_max = RTSX_SDCLK_208MHZ;
730 sc->rtsx_host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_HSPEED |
733 sc->rtsx_host.caps |= MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104;
734 if (sc->rtsx_device_id == RTSX_RTS5209)
735 sc->rtsx_host.caps |= MMC_CAP_8_BIT_DATA;
736 pci_find_cap(sc->rtsx_dev, PCIY_EXPRESS, &(sc->rtsx_pcie_cap));
741 switch (sc->rtsx_device_id) {
744 RTSX_READ(sc, RTSX_DUMMY_REG, &version);
746 sc->rtsx_flags |= RTSX_F_VERSION_C;
750 RTSX_READ(sc, RTSX_DUMMY_REG, &version);
752 sc->rtsx_flags |= RTSX_F_VERSION_A;
756 RTSX_READ(sc, RTSX_DUMMY_REG, &version);
758 sc->rtsx_flags |= RTSX_F_VERSION_A;
761 RTSX_READ(sc, RTSX_RTL8411B_PACKAGE, &version);
763 sc->rtsx_flags |= RTSX_F_8411B_QFN48;
776 sc->rtsx_card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
777 switch (sc->rtsx_device_id) {
782 sc->rtsx_card_drive_sel = RTSX_RTS5209_CARD_DRIVE_DEFAULT;
783 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D;
784 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);
786 sc->rtsx_card_drive_sel = (reg >> 8) & 0x3F;
787 sc->rtsx_sd30_drive_sel_3v3 = reg & 0x07;
788 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
789 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
791 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
792 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n",
793 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3);
797 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B;
798 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
800 sc->rtsx_card_drive_sel &= 0x3F;
801 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6;
802 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);
803 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03;
805 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET;
806 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
807 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
809 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
810 device_printf(sc->rtsx_dev,
812 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3,
813 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false");
816 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D;
817 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
819 sc->rtsx_card_drive_sel &= 0x3F;
820 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6;
821 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);
822 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive((reg >> 5) & 0x03);
823 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
824 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
826 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
827 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n",
828 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3);
833 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B;
834 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
836 sc->rtsx_card_drive_sel &= 0x3F;
837 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6;
838 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);
839 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03;
841 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET;
842 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
843 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
845 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
846 device_printf(sc->rtsx_dev,
848 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3,
849 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false");
853 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT;
854 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D;
855 reg1 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
857 sc->rtsx_card_drive_sel &= 0x3F;
858 sc->rtsx_card_drive_sel |= ((reg1 >> 25) & 0x01) << 6;
859 reg3 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG3, 1);
860 sc->rtsx_sd30_drive_sel_3v3 = (reg3 >> 5) & 0x07;
861 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
862 device_printf(sc->rtsx_dev, "pci_read_config() error - reg1: 0x%08x\n", reg1);
864 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
865 device_printf(sc->rtsx_dev,
867 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3);
870 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT;
871 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D;
872 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
874 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive(reg & 0x03);
875 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
876 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
878 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
879 device_printf(sc->rtsx_dev,
881 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3);
885 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
886 device_printf(sc->rtsx_dev, "rtsx_init() rtsx_flags: 0x%04x\n", sc->rtsx_flags);
889 sc->rtsx_intr_enabled = RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN;
890 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled);
893 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN);
898 val = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, 1);
899 pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, val & 0xfc, 1);
904 switch (sc->rtsx_device_id) {
907 if ((error = rtsx_write_phy(sc, 0x00, 0xB966)))
911 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN);
914 if ((error = rtsx_write_phy(sc, 0x00, 0xBA42)))
919 if ((error = rtsx_write_phy(sc, 0x00, 0xBA42)))
923 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, RTSX_D3_DELINK_MODE_EN);
924 if (sc->rtsx_flags & RTSX_F_VERSION_A) {
925 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR2, RTSX_PHY_RCR2_INIT_27S)))
928 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR1, RTSX_PHY_RCR1_INIT_27S)))
930 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD0, RTSX_PHY_FLD0_INIT_27S)))
932 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD3, RTSX_PHY_FLD3_INIT_27S)))
934 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD4, RTSX_PHY_FLD4_INIT_27S)))
938 if ((error = rtsx_write_phy(sc, RTSX__PHY_FLD0,
943 if ((error = rtsx_write_phy(sc, RTSX__PHY_ANA03,
947 if (sc->rtsx_flags & RTSX_F_VERSION_A)
948 if ((error = rtsx_write_phy(sc, RTSX__PHY_REV0,
954 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN);
955 if ((error = rtsx_write_phy(sc, RTSX_PHY_REV,
963 if ((error = rtsx_write_phy(sc, RTSX_PHY_BPCR,
967 if ((error = rtsx_write_phy(sc, RTSX_PHY_PCR,
972 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR2,
977 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD4,
983 if ((error = rtsx_write_phy(sc, RTSX_PHY_RDR,
986 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR1,
989 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD3,
993 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE,
1002 RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07);
1005 RTSX_CLR(sc, RTSX_HOST_SLEEP_STATE,
1009 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL);
1012 RTSX_CLR(sc, RTSX_CHANGE_LINK_STATE,
1016 RTSX_WRITE(sc, RTSX_CARD_DRIVE_SEL, sc->rtsx_card_drive_sel);
1019 RTSX_WRITE(sc, RTSX_SSC_CTL1, RTSX_SSC_8X_EN | RTSX_SSC_SEL_4M);
1020 RTSX_WRITE(sc, RTSX_SSC_CTL2, 0x12);
1023 RTSX_BITOP(sc, RTSX_CHANGE_LINK_STATE, 0x16, RTSX_MAC_PHY_RST_N_DBG);
1026 RTSX_BITOP(sc, RTSX_IRQSTAT0, RTSX_LINK_READY_INT, RTSX_LINK_READY_INT);
1030 RTSX_WRITE(sc, RTSX_PERST_GLITCH_WIDTH, 0x80);
1033 RTSX_CLR(sc, RTSX_RCCTL, RTSX_RCCTL_F_2M);
1036 RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR);
1038 switch (sc->rtsx_device_id) {
1041 RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, 1, 1);
1046 RTSX_BITOP(sc, RTSX_FPDCTL, RTSX_SD_OC_POWER_DOWN, RTSX_SD_OC_POWER_DOWN);
1049 pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL + 1, 1, 1);
1052 pci_write_config(sc->rtsx_dev, 0x70F, 0x5B, 1);
1057 switch (sc->rtsx_device_id) {
1061 RTSX_WRITE(sc, RTSX_CARD_GPIO, 0x03);
1063 RTSX_CLR(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK);
1065 RTSX_BITOP(sc, RTSX_PETXCFG, 0x08, 0x08);
1067 RTSX_WRITE(sc, RTSX_CARD_GPIO_DIR, 0x03);
1069 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3);
1073 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON);
1075 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM);
1077 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33);
1078 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3);
1080 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD);
1082 cap = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_DEVICE_CTL2, 2);
1084 RTSX_WRITE(sc, RTSX_LTR_CTL, 0xa3);
1086 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_ENABLE);
1088 if ((error = rtsx_rts5227_fill_driving(sc)))
1091 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET)
1092 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0xB8);
1094 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0x88);
1095 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN);
1097 RTSX_BITOP(sc, RTSX_PM_CTRL3, RTSX_PM_WAKE_EN, RTSX_PM_WAKE_EN);
1101 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON);
1106 RTSX_BITOP(sc, RTSX_PETXCFG, 0x08, 0x08);
1108 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33);
1109 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3);
1111 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD);
1113 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3);
1118 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON);
1120 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM);
1122 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33);
1123 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3);
1125 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD);
1127 cap = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_DEVICE_CTL2, 2);
1129 RTSX_WRITE(sc, RTSX_LTR_CTL, 0xa3);
1131 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_ENABLE);
1133 if ((error = rtsx_rts5227_fill_driving(sc)))
1136 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET)
1137 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0xB8);
1139 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0x88);
1140 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, 0x10);
1143 RTSX_BITOP(sc, RTSX_FUNC_FORCE_CTL,
1145 RTSX_BITOP(sc, RTSX_PCLK_CTL, 0x04, 0x04);
1146 RTSX_BITOP(sc, RTSX_PM_EVENT_DEBUG,
1148 RTSX_WRITE(sc, RTSX_PM_CLK_FORCE_CTL, 0x11);
1153 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xff);
1155 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON);
1157 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM);
1159 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33);
1160 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3);
1162 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD);
1164 if ((error = rtsx_rts5249_fill_driving(sc)))
1167 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET)
1168 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0);
1170 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80);
1173 RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL);
1174 if (sc->rtsx_flags & RTSX_F_VERSION_A) {
1175 RTSX_WRITE(sc, RTSX_L1SUB_CONFIG2, RTSX_L1SUB_AUTO_CFG);
1176 RTSX_BITOP(sc, RTSX_RREF_CFG,
1178 RTSX_BITOP(sc, RTSX_LDO_VIO_CFG,
1180 RTSX_BITOP(sc, RTSX_LDO_DV12S_CFG,
1182 RTSX_BITOP(sc, RTSX_LDO_AV12S_CFG,
1184 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0,
1186 RTSX_BITOP(sc, RTSX_OOBS_CONFIG,
1192 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xff);
1194 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON);
1196 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM);
1198 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33);
1199 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3);
1201 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD);
1203 if ((error = rtsx_rts5249_fill_driving(sc)))
1206 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET)
1207 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0);
1209 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80);
1213 RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07);
1214 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, 0x5D);
1216 RTSX_WRITE(sc, RTSX_RTS5260_AUTOLOAD_CFG4, RTSX_RTS5260_MIMO_DISABLE);
1218 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33);
1220 RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL);
1222 RTSX_BITOP(sc, RTSX_L1SUB_CONFIG1, RTSX_AUX_CLK_ACTIVE_SEL_MASK, RTSX_MAC_CKSW_DONE);
1224 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xFF);
1225 RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, RTSX_CLK_PM_EN, RTSX_CLK_PM_EN);
1226 RTSX_WRITE(sc, RTSX_PWD_SUSPEND_EN, 0xFF);
1227 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_PWR_GATE_EN, RTSX_PWR_GATE_EN);
1228 RTSX_BITOP(sc, RTSX_REG_VREF, RTSX_PWD_SUSPND_EN, RTSX_PWD_SUSPND_EN);
1229 RTSX_BITOP(sc, RTSX_RBCTL, RTSX_U_AUTO_DMA_EN_MASK, RTSX_U_AUTO_DMA_DISABLE);
1230 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET)
1231 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0);
1233 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80);
1234 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_DISABLE);
1236 RTSX_CLR(sc, RTSX_RTS5260_DVCC_CTRL, RTSX_RTS5260_DVCC_OCP_EN | RTSX_RTS5260_DVCC_OCP_CL_EN);
1239 RTSX_BITOP(sc, RTSX_PETXCFG, RTSX_FORCE_CLKREQ_DELINK_MASK, RTSX_FORCE_CLKREQ_LOW);
1241 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, 0x10);
1245 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3);
1246 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE,
1250 if (sc->rtsx_flags & RTSX_F_8411B_QFN48)
1251 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5);
1252 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3);
1254 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE,
1257 RTSX_BITOP(sc, RTSX_FUNC_FORCE_CTL, 0x06, 0x00);
1262 rtsx_bus_power_off(sc);
1263 rtsx_set_sd_timing(sc, bus_timing_normal);
1264 rtsx_set_sd_clock(sc, 0);
1285 rtsx_rts5227_fill_driving(struct rtsx_softc *sc) argument
1293 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]);
1294 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]);
1295 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]);
1302 rtsx_rts5249_fill_driving(struct rtsx_softc *sc) argument
1310 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]);
1311 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]);
1312 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]);
1318 rtsx_rts5260_fill_driving(struct rtsx_softc *sc) argument
1326 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]);
1327 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]);
1328 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]);
1334 rtsx_read(struct rtsx_softc *sc, uint16_t addr, uint8_t *val) argument
1341 WRITE4(sc, RTSX_HAIMR, arg);
1344 reg = READ4(sc, RTSX_HAIMR);
1353 device_printf(sc->rtsx_dev, "rtsx_read(0x%x) timeout\n", arg);
1359 rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val) argument
1364 RTSX_WRITE(sc, RTSX_CFGADDR0, addr);
1365 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8);
1366 RTSX_WRITE(sc, RTSX_CFGRWCTL, RTSX_CFG_BUSY | (func & 0x03 << 4));
1369 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl);
1377 RTSX_READ(sc, RTSX_CFGDATA0, &data0);
1378 RTSX_READ(sc, RTSX_CFGDATA1, &data1);
1379 RTSX_READ(sc, RTSX_CFGDATA2, &data2);
1380 RTSX_READ(sc, RTSX_CFGDATA3, &data3);
1388 rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val) argument
1397 WRITE4(sc, RTSX_HAIMR, arg);
1400 reg = READ4(sc, RTSX_HAIMR);
1403 device_printf(sc->rtsx_dev, "rtsx_write(0x%x) error reg=0x%x\n", arg, reg);
1409 device_printf(sc->rtsx_dev, "rtsx_write(0x%x) timeout\n", arg);
1415 rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val) argument
1420 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr);
1421 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY | RTSX_PHY_READ);
1424 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl);
1431 RTSX_READ(sc, RTSX_PHY_DATA0, &data0);
1432 RTSX_READ(sc, RTSX_PHY_DATA1, &data1);
1439 rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val) argument
1444 RTSX_WRITE(sc, RTSX_PHY_DATA0, val);
1445 RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8);
1446 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr);
1447 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY | RTSX_PHY_WRITE);
1450 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl);
1464 rtsx_bus_power_off(struct rtsx_softc *sc) argument
1466 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
1467 device_printf(sc->rtsx_dev, "rtsx_bus_power_off()\n");
1470 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN);
1473 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN);
1476 switch (sc->rtsx_device_id) {
1478 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK,
1480 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF);
1485 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK,
1487 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK);
1490 rtsx_stop_cmd(sc);
1492 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1);
1493 RTSX_BITOP(sc, RTSX_LDO_DV18_CFG, RTSX_DV331812_MASK, RTSX_DV331812_33);
1494 RTSX_CLR(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8);
1495 rtsx_rts5260_fill_driving(sc);
1497 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_OFF);
1498 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWEROFF);
1503 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK,
1505 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB,
1509 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK);
1510 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF);
1511 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_PMOS_STRG_800mA);
1516 switch (sc->rtsx_device_id) {
1518 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_DISABLE12);
1519 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12);
1520 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3);
1524 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12);
1525 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3);
1528 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12);
1529 if (sc->rtsx_flags & RTSX_F_VERSION_C)
1530 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3_TYPE_C);
1532 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3);
1537 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66);
1538 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12);
1539 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3);
1540 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x55);
1544 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65);
1545 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55);
1546 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0x95);
1547 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09);
1548 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x05);
1549 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04);
1552 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) {
1553 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55);
1554 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5);
1555 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15);
1557 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65);
1558 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55);
1559 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd5);
1560 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59);
1561 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55);
1562 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15);
1571 rtsx_bus_power_on(struct rtsx_softc *sc) argument
1573 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
1574 device_printf(sc->rtsx_dev, "rtsx_bus_power_on()\n");
1577 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL);
1578 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD);
1581 RTSX_BITOP(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN, RTSX_SD_CLK_EN);
1584 switch (sc->rtsx_device_id) {
1586 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_ENABLE12);
1587 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12);
1588 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3);
1592 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12);
1593 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3);
1596 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12);
1597 if (sc->rtsx_flags & RTSX_F_VERSION_C)
1598 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3_TYPE_C);
1600 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3);
1605 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66);
1606 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12);
1607 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3);
1608 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0xaa);
1612 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa);
1613 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa);
1614 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xa9);
1615 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09);
1616 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x09);
1617 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04);
1620 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) {
1621 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa);
1622 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf9);
1623 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x19);
1625 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa);
1626 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa);
1627 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd9);
1628 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59);
1629 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55);
1630 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15);
1639 switch (sc->rtsx_device_id) {
1642 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON);
1643 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC2);
1648 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON);
1649 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_ON);
1654 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON);
1655 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1);
1660 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON);
1661 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK,
1663 RTSX_BITOP(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN, RTSX_SD_OUTPUT_EN);
1664 RTSX_BITOP(sc, RTSX_CARD_OE, RTSX_MS_OUTPUT_EN, RTSX_MS_OUTPUT_EN);
1668 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON);
1669 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1);
1674 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON);
1675 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK,
1679 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_VCC_TUNE_MASK, RTSX_LDO_VCC_3V3);
1682 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON);
1683 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1);
1688 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON);
1689 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK,
1693 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1);
1694 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33);
1695 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_ON);
1696 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWERON);
1700 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK | RTSX_SD_ASYNC_FIFO_NOT_RST,
1702 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CLK_LOW_FREQ);
1703 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE,
1705 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ);
1708 RTSX_WRITE(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128 | RTSX_SD20_MODE);
1709 RTSX_WRITE(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_POS_EDGE);
1710 RTSX_CLR(sc, RTSX_SD_PUSH_POINT_CTL, 0xff);
1711 RTSX_BITOP(sc, RTSX_CARD_STOP, RTSX_SD_STOP | RTSX_SD_CLR_ERR,
1714 RTSX_CLR(sc, RTSX_SD_CFG3, RTSX_SD30_CLK_END_EN);
1715 RTSX_CLR(sc, RTSX_REG_SD_STOP_SDCLK_CFG,
1717 RTSX_CLR(sc, RTSX_REG_PRE_RW_MODE, RTSX_EN_INFINITE_MODE);
1722 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK,
1724 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB,
1727 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK,
1730 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK,
1733 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK,
1735 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB,
1741 RTSX_WRITE(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN);
1752 rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width) argument
1769 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK, bus_width);
1771 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
1777 device_printf(sc->rtsx_dev, "Setting bus width to %s\n", busw[bus_width]);
1783 rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing) argument
1785 if (timing == bus_timing_hs && sc->rtsx_force_timing) {
1787 sc->rtsx_ios_timing = timing;
1790 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
1791 device_printf(sc->rtsx_dev, "rtsx_set_sd_timing(%u)\n", timing);
1796 sc->rtsx_double_clk = false;
1797 sc->rtsx_vpclk = true;
1798 RTSX_BITOP(sc, RTSX_SD_CFG1, 0x0c | RTSX_SD_ASYNC_FIFO_NOT_RST,
1800 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ);
1801 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE,
1803 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ);
1806 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK, RTSX_SD20_MODE);
1807 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ);
1808 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE,
1810 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ);
1812 RTSX_BITOP(sc, RTSX_SD_PUSH_POINT_CTL,
1814 RTSX_BITOP(sc, RTSX_SD_SAMPLE_POINT_CTL,
1818 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK, RTSX_SD20_MODE);
1819 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ);
1820 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE,
1822 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ);
1824 RTSX_WRITE(sc, RTSX_SD_PUSH_POINT_CTL, RTSX_SD20_TX_NEG_EDGE);
1825 RTSX_BITOP(sc, RTSX_SD_SAMPLE_POINT_CTL,
1838 rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq) argument
1844 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
1845 device_printf(sc->rtsx_dev, "rtsx_set_sd_clock(%u)\n", freq);
1848 error = rtsx_stop_sd_clock(sc);
1852 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_500K;
1853 sc->rtsx_discovery_mode = (freq <= 1000000) ? true : false;
1855 if (sc->rtsx_discovery_mode) {
1862 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, clk_divider);
1865 if (sc->rtsx_discovery_mode || !sc->rtsx_double_clk)
1870 switch (sc->rtsx_device_id) {
1890 switch (sc->rtsx_device_id) {
1903 if (sc->rtsx_double_clk && sc->rtsx_ssc_depth > 1)
1904 sc->rtsx_ssc_depth -= 1;
1907 if (sc->rtsx_ssc_depth > (div - 1))
1908 sc->rtsx_ssc_depth -= (div - 1);
1910 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_4M;
1914 error = rtsx_switch_sd_clock(sc, clk, n, div, mcu);
1920 rtsx_stop_sd_clock(struct rtsx_softc *sc) argument
1922 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL);
1923 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP);
1929 rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu) argument
1931 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
1932 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - discovery-mode is %s, ssc_depth: %d\n",
1933 (sc->rtsx_discovery_mode) ? "true" : "false", sc->rtsx_ssc_depth);
1934 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - clk: %d, n: %d, div: %d, mcu: %d\n",
1938 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ);
1939 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu);
1940 RTSX_CLR(sc, RTSX_SSC_CTL1, RTSX_RSTB);
1941 RTSX_BITOP(sc, RTSX_SSC_CTL2, RTSX_SSC_DEPTH_MASK, sc->rtsx_ssc_depth);
1942 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, n);
1943 RTSX_BITOP(sc, RTSX_SSC_CTL1, RTSX_RSTB, RTSX_RSTB);
1944 if (sc->rtsx_vpclk) {
1945 RTSX_CLR(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET);
1946 RTSX_BITOP(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET);
1952 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ);
1959 rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point) argument
1961 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
1962 device_printf(sc->rtsx_dev, "rtsx_sd_change_tx_phase() - sample_point: %d\n", sample_point);
1964 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK);
1965 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_SELECT_MASK, sample_point);
1966 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, 0);
1967 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET);
1968 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0);
1969 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0);
1973 rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point) argument
1975 if (sc->rtsx_debug_mask & RTSX_DEBUG_TUNING)
1976 device_printf(sc->rtsx_dev, "rtsx_sd_change_rx_phase() - sample_point: %d\n", sample_point);
1978 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK);
1979 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_SELECT_MASK, sample_point);
1980 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, 0);
1981 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET);
1982 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0);
1983 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0);
1987 rtsx_sd_tuning_rx_phase(struct rtsx_softc *sc, uint32_t *phase_map) argument
1994 error = rtsx_sd_tuning_rx_cmd(sc, (uint8_t)i);
2003 rtsx_sd_tuning_rx_cmd(struct rtsx_softc *sc, uint8_t sample_point) argument
2013 RTSX_LOCK(sc);
2015 sc->rtsx_req = &req;
2017 rtsx_sd_change_rx_phase(sc, sample_point);
2019 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN,
2022 rtsx_init_cmd(sc, &cmd);
2023 rtsx_set_cmd_data_len(sc, 1, 0x40);
2024 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff,
2027 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER,
2029 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER,
2033 sc->rtsx_intr_trans_ok = rtsx_sd_tuning_rx_cmd_wakeup;
2034 sc->rtsx_intr_trans_ko = rtsx_sd_tuning_rx_cmd_wakeup;
2037 rtsx_send_cmd(sc);
2039 error = rtsx_sd_tuning_rx_cmd_wait(sc, &cmd);
2042 if (sc->rtsx_debug_mask & RTSX_DEBUG_TUNING)
2043 device_printf(sc->rtsx_dev, "rtsx_sd_tuning_rx_cmd() - error: %d\n", error);
2044 rtsx_sd_wait_data_idle(sc);
2045 rtsx_clear_error(sc);
2047 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 0);
2049 sc->rtsx_req = NULL;
2051 RTSX_UNLOCK(sc);
2057 rtsx_sd_tuning_rx_cmd_wait(struct rtsx_softc *sc, struct mmc_command *cmd) argument
2062 status = sc->rtsx_intr_status & mask;
2064 …if (msleep(&sc->rtsx_intr_status, &sc->rtsx_mtx, 0, "rtsxintr", sc->rtsx_timeout_cmd) == EWOULDBLO…
2068 status = sc->rtsx_intr_status & mask;
2074 rtsx_sd_tuning_rx_cmd_wakeup(struct rtsx_softc *sc) argument
2076 wakeup(&sc->rtsx_intr_status);
2080 rtsx_sd_wait_data_idle(struct rtsx_softc *sc) argument
2086 rtsx_read(sc, RTSX_SD_DATA_STATE, &val);
2094 rtsx_sd_search_final_rx_phase(struct rtsx_softc *sc, uint32_t phase_map) argument
2111 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
2112 device_printf(sc->rtsx_dev,
2134 rtsx_led_enable(struct rtsx_softc *sc)
2136 switch (sc->rtsx_device_id) {
2138 RTSX_CLR(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF);
2139 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK,
2143 RTSX_CLR(sc, RTSX_GPIO_CTL, 0x01);
2144 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK,
2148 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON);
2149 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK);
2157 rtsx_led_disable(struct rtsx_softc *sc)
2159 switch (sc->rtsx_device_id) {
2161 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN);
2162 RTSX_WRITE(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF);
2165 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN);
2166 RTSX_SET(sc, RTSX_GPIO_CTL, 0x01);
2169 RTSX_CLR(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK);
2170 RTSX_CLR(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON);
2209 rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd) argument
2211 sc->rtsx_cmd_index = 0;
2212 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD0,
2214 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD1,
2216 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD2,
2218 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD3,
2220 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD4,
2228 rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg, argument
2231 KASSERT(sc->rtsx_cmd_index < RTSX_HOSTCMD_MAX,
2232 ("rtsx: Too many host commands (%d)\n", sc->rtsx_cmd_index));
2234 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem);
2235 cmd_buffer[sc->rtsx_cmd_index++] =
2246 rtsx_set_cmd_data_len(struct rtsx_softc *sc, uint16_t block_cnt, uint16_t byte_cnt) argument
2248 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L,
2250 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H,
2252 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L,
2254 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H,
2262 rtsx_send_cmd(struct rtsx_softc *sc) argument
2264 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
2265 device_printf(sc->rtsx_dev, "rtsx_send_cmd()\n");
2267 sc->rtsx_intr_status = 0;
2270 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREREAD);
2271 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREWRITE);
2274 WRITE4(sc, RTSX_HCBAR, (uint32_t)sc->rtsx_cmd_buffer);
2275 WRITE4(sc, RTSX_HCBCTLR,
2276 ((sc->rtsx_cmd_index * 4) & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP);
2283 rtsx_stop_cmd(struct rtsx_softc *sc) argument
2286 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD);
2289 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA);
2291 switch (sc->rtsx_device_id) {
2293 rtsx_write(sc, RTSX_RTS5260_DMA_RST_CTL_0,
2296 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH);
2299 rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST);
2301 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH);
2310 rtsx_clear_error(struct rtsx_softc *sc) argument
2313 rtsx_write(sc, RTSX_CARD_STOP, RTSX_SD_STOP | RTSX_SD_CLR_ERR,
2321 rtsx_req_done(struct rtsx_softc *sc) argument
2328 req = sc->rtsx_req;
2332 sc->rtsx_read_count++;
2335 sc->rtsx_write_count++;
2337 rtsx_clear_error(sc);
2339 callout_stop(&sc->rtsx_timeout_callout);
2340 sc->rtsx_req = NULL;
2342 ccb = sc->rtsx_ccb;
2343 sc->rtsx_ccb = NULL;
2355 rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd) argument
2360 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
2361 device_printf(sc->rtsx_dev, "rtsx_send_req() - CMD%d\n", cmd->opcode);
2366 device_printf(sc->rtsx_dev, "Unknown rsp_type: 0x%lx\n", (cmd->flags & MMC_RSP_MASK));
2371 rtsx_init_cmd(sc, cmd);
2374 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, rsp_type);
2377 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE,
2381 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER,
2383 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER,
2391 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0);
2395 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0);
2397 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, RTSX_SD_STAT1, 0, 0);
2400 if (sc->rtsx_intr_trans_ok == NULL)
2401 sc->rtsx_intr_trans_ok = rtsx_ret_resp;
2404 rtsx_send_cmd(sc);
2414 rtsx_ret_resp(struct rtsx_softc *sc) argument
2418 cmd = sc->rtsx_req->cmd;
2419 rtsx_set_resp(sc, cmd);
2420 rtsx_req_done(sc);
2427 rtsx_set_resp(struct rtsx_softc *sc, struct mmc_command *cmd) argument
2434 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD);
2435 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE);
2439 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem);
2441 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) {
2442 device_printf(sc->rtsx_dev, "cmd_buffer: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
2470 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
2471 device_printf(sc->rtsx_dev, "cmd->resp: 0x%08x 0x%08x 0x%08x 0x%08x\n",
2480 rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd) argument
2493 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
2494 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - %s xfer: %ld bytes with block size %ld\n",
2499 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - length too large: %ld > 512\n",
2506 if (sc->rtsx_discovery_mode)
2507 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_0);
2509 rtsx_init_cmd(sc, cmd);
2512 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len);
2515 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff,
2520 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE,
2524 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER,
2526 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER,
2530 sc->rtsx_intr_trans_ok = rtsx_ask_ppbuf_part1;
2533 rtsx_send_cmd(sc);
2536 sc->rtsx_intr_trans_ok = rtsx_put_ppbuf_part1;
2539 rtsx_send_req(sc, cmd);
2550 rtsx_ask_ppbuf_part1(struct rtsx_softc *sc) argument
2557 cmd = sc->rtsx_req->cmd;
2560 sc->rtsx_cmd_index = 0;
2562 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0);
2566 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part1;
2569 rtsx_send_cmd(sc);
2577 rtsx_get_ppbuf_part1(struct rtsx_softc *sc) argument
2583 cmd = sc->rtsx_req->cmd;
2588 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD);
2589 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE);
2591 memcpy(ptr, sc->rtsx_cmd_dmamem, len);
2600 sc->rtsx_cmd_index = 0;
2602 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0);
2606 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part2;
2609 rtsx_send_cmd(sc);
2611 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD && cmd->opcode == ACMD_SEND_SCR) {
2613 device_printf(sc->rtsx_dev, "SCR: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2618 if (sc->rtsx_discovery_mode)
2619 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128);
2621 rtsx_req_done(sc);
2630 rtsx_get_ppbuf_part2(struct rtsx_softc *sc) argument
2636 cmd = sc->rtsx_req->cmd;
2642 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD);
2643 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE);
2645 memcpy(ptr, sc->rtsx_cmd_dmamem, len);
2647 if (sc->rtsx_discovery_mode)
2648 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128);
2650 rtsx_req_done(sc);
2658 rtsx_put_ppbuf_part1(struct rtsx_softc *sc) argument
2666 cmd = sc->rtsx_req->cmd;
2670 rtsx_set_resp(sc, cmd);
2672 sc->rtsx_cmd_index = 0;
2674 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr);
2680 sc->rtsx_intr_trans_ok = rtsx_put_ppbuf_part2;
2682 sc->rtsx_intr_trans_ok = rtsx_write_ppbuf;
2685 rtsx_send_cmd(sc);
2693 rtsx_put_ppbuf_part2(struct rtsx_softc *sc) argument
2701 cmd = sc->rtsx_req->cmd;
2706 sc->rtsx_cmd_index = 0;
2708 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr);
2713 sc->rtsx_intr_trans_ok = rtsx_write_ppbuf;
2716 rtsx_send_cmd(sc);
2724 rtsx_write_ppbuf(struct rtsx_softc *sc) argument
2728 cmd = sc->rtsx_req->cmd;
2730 sc->rtsx_cmd_index = 0;
2733 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len);
2736 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff,
2740 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 0xff,
2742 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER,
2746 sc->rtsx_intr_trans_ok = rtsx_req_done;
2749 rtsx_send_cmd(sc);
2756 rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd) argument
2763 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
2764 device_printf(sc->rtsx_dev, "rtsx_xfer() - %s xfer: %ld bytes with block size %ld\n",
2769 device_printf(sc->rtsx_dev, "rtsx_xfer() length too large: %ld > %ld\n",
2777 sc->rtsx_intr_trans_ok = rtsx_xfer_begin;
2780 rtsx_send_req(sc, cmd);
2782 rtsx_xfer_start(sc);
2793 rtsx_xfer_begin(struct rtsx_softc *sc) argument
2797 cmd = sc->rtsx_req->cmd;
2799 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
2800 device_printf(sc->rtsx_dev, "rtsx_xfer_begin() - CMD%d\n", cmd->opcode);
2802 rtsx_set_resp(sc, cmd);
2803 rtsx_xfer_start(sc);
2810 rtsx_xfer_start(struct rtsx_softc *sc) argument
2818 cmd = sc->rtsx_req->cmd;
2836 rtsx_init_cmd(sc, cmd);
2847 sc->rtsx_cmd_index = 0;
2851 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len);
2854 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0,
2856 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC3,
2858 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC2,
2860 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC1,
2862 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC0,
2864 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMACTL,
2869 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE,
2873 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, cfg2);
2876 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER,
2878 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER,
2882 rtsx_send_cmd(sc);
2885 memcpy(sc->rtsx_data_dmamem, cmd->data->data, cmd->data->len);
2888 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_PREREAD);
2889 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_PREWRITE);
2892 sc->rtsx_intr_trans_ok = rtsx_xfer_finish;
2895 WRITE4(sc, RTSX_HDBAR, sc->rtsx_data_buffer);
2896 WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) |
2905 rtsx_xfer_finish(struct rtsx_softc *sc) argument
2910 cmd = sc->rtsx_req->cmd;
2912 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
2913 device_printf(sc->rtsx_dev, "rtsx_xfer_finish() - CMD%d\n", cmd->opcode);
2918 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTREAD);
2919 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTWRITE);
2922 memcpy(cmd->data->data, sc->rtsx_data_dmamem, cmd->data->len);
2923 rtsx_req_done(sc);
2927 sc->rtsx_intr_trans_ok = NULL;
2928 rtsx_send_req(sc, sc->rtsx_req->stop);
2938 struct rtsx_softc *sc; local
2940 sc = (struct rtsx_softc *)arg;
2941 if (sc->rtsx_req != NULL) {
2942 device_printf(sc->rtsx_dev, "Controller timeout for CMD%u\n",
2943 sc->rtsx_req->cmd->opcode);
2944 sc->rtsx_req->cmd->error = MMC_ERR_TIMEOUT;
2945 rtsx_stop_cmd(sc);
2946 rtsx_req_done(sc);
2948 device_printf(sc->rtsx_dev, "Controller timeout!\n");
2956 struct rtsx_softc *sc; local
2958 sc = device_get_softc(dev);
2960 cts->host_ocr = sc->rtsx_host.host_ocr;
2961 cts->host_f_min = sc->rtsx_host.f_min;
2962 cts->host_f_max = sc->rtsx_host.f_max;
2963 cts->host_caps = sc->rtsx_host.caps;
2965 memcpy(&cts->ios, &sc->rtsx_host.ios, sizeof(struct mmc_ios));
2976 struct rtsx_softc *sc; local
2980 sc = device_get_softc(dev);
2982 ios = &sc->rtsx_host.ios;
2988 sc->rtsx_ios_clock = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
2989 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
2990 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - clock: %u\n", ios->clock);
2994 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
2995 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vdd: %d\n", ios->vdd);
2999 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
3000 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - chip_select: %d\n", ios->chip_select);
3004 sc->rtsx_ios_bus_width = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
3005 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
3006 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus width: %d\n", ios->bus_width);
3010 sc->rtsx_ios_power_mode = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
3011 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
3012 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - power mode: %d\n", ios->power_mode);
3016 sc->rtsx_ios_timing = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
3017 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
3018 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - timing: %d\n", ios->timing);
3022 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
3023 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus mode: %d\n", ios->bus_mode);
3028 sc->rtsx_ios_vccq = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
3029 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
3030 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vccq: %d\n", ios->vccq);
3033 if (rtsx_mmcbr_update_ios(sc->rtsx_dev, NULL) == 0)
3045 struct rtsx_softc *sc; local
3047 sc = device_get_softc(dev);
3049 RTSX_LOCK(sc);
3050 if (sc->rtsx_ccb != NULL) {
3051 RTSX_UNLOCK(sc);
3054 sc->rtsx_ccb = ccb;
3055 sc->rtsx_cam_req.cmd = &ccb->mmcio.cmd;
3056 sc->rtsx_cam_req.stop = &ccb->mmcio.stop;
3057 RTSX_UNLOCK(sc);
3059 rtsx_mmcbr_request(sc->rtsx_dev, NULL, &sc->rtsx_cam_req);
3067 struct rtsx_softc *sc; local
3069 sc = device_get_softc(bus);
3072 *result = sc->rtsx_host.ios.bus_mode;
3075 *result = sc->rtsx_host.ios.bus_width;
3078 *result = sc->rtsx_host.ios.chip_select;
3081 *result = sc->rtsx_host.ios.clock;
3084 *result = sc->rtsx_host.f_min;
3087 *result = sc->rtsx_host.f_max;
3090 *result = sc->rtsx_host.host_ocr;
3093 *result = sc->rtsx_host.mode;
3096 *result = sc->rtsx_host.ocr;
3099 *result = sc->rtsx_host.ios.power_mode;
3102 *result = sc->rtsx_host.ios.vdd;
3105 *result = sc->rtsx_host.ios.vccq;
3108 *result = sc->rtsx_host.caps;
3111 *result = sc->rtsx_host.ios.timing;
3122 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
3132 struct rtsx_softc *sc; local
3134 sc = device_get_softc(bus);
3135 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
3141 sc->rtsx_host.ios.bus_mode = value;
3144 sc->rtsx_host.ios.bus_width = value;
3145 sc->rtsx_ios_bus_width = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */
3148 sc->rtsx_host.ios.chip_select = value;
3151 sc->rtsx_host.ios.clock = value;
3152 sc->rtsx_ios_clock = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */
3155 sc->rtsx_host.mode = value;
3158 sc->rtsx_host.ocr = value;
3161 sc->rtsx_host.ios.power_mode = value;
3162 sc->rtsx_ios_power_mode = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */
3165 sc->rtsx_host.ios.vdd = value;
3168 sc->rtsx_host.ios.vccq = value;
3169 sc->rtsx_ios_vccq = value; /* rtsx_mmcbr_switch_vccq() will be called by mmc.c (MMCCAM undef). */
3172 sc->rtsx_host.ios.timing = value;
3173 sc->rtsx_ios_timing = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */
3193 struct rtsx_softc *sc; local
3197 sc = device_get_softc(bus);
3198 ios = &sc->rtsx_host.ios;
3200 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
3204 if (sc->rtsx_ios_bus_width < 0) {
3205 sc->rtsx_ios_bus_width = ios->bus_width;
3206 if ((error = rtsx_set_bus_width(sc, ios->bus_width)))
3211 if (sc->rtsx_ios_power_mode < 0) {
3212 sc->rtsx_ios_power_mode = ios->power_mode;
3215 if ((error = rtsx_bus_power_off(sc)))
3219 if ((error = rtsx_bus_power_on(sc)))
3223 if ((error = rtsx_bus_power_on(sc)))
3229 sc->rtsx_double_clk = true;
3230 sc->rtsx_vpclk = false;
3233 if (sc->rtsx_ios_timing < 0) {
3234 sc->rtsx_ios_timing = ios->timing;
3235 if ((error = rtsx_set_sd_timing(sc, ios->timing)))
3240 if (sc->rtsx_ios_clock < 0) {
3241 sc->rtsx_ios_clock = ios->clock;
3242 if ((error = rtsx_set_sd_clock(sc, ios->clock)))
3247 if (sc->rtsx_ios_vccq < 0) {
3248 sc->rtsx_ios_vccq = ios->vccq;
3249 if ((error = rtsx_mmcbr_switch_vccq(sc->rtsx_dev, NULL)))
3262 struct rtsx_softc *sc; local
3266 sc = device_get_softc(bus);
3268 switch (sc->rtsx_host.ios.vccq) {
3281 switch (sc->rtsx_device_id) {
3284 if ((error = rtsx_write_phy(sc, 0x08, 0x4FE4)))
3286 if ((error = rtsx_rts5227_fill_driving(sc)))
3291 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3);
3292 if ((error = rtsx_write_phy(sc, 0x08, 0x4FE4)))
3296 if ((error = rtsx_write_phy(sc, 0x08, 0x57E4)))
3298 if ((error = rtsx_rts5227_fill_driving(sc)))
3302 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_LDO_D3318_MASK, RTSX_LDO_D3318_33V);
3303 RTSX_BITOP(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8, 0);
3304 if ((error = rtsx_rts5249_fill_driving(sc)))
3308 if ((error = rtsx_read_phy(sc, RTSX_PHY_TUNE, &val)))
3310 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE,
3313 if ((error = rtsx_rts5249_fill_driving(sc)))
3317 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1);
3318 RTSX_BITOP(sc, RTSX_LDO_DV18_CFG, RTSX_DV331812_MASK, RTSX_DV331812_33);
3319 RTSX_CLR(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8);
3320 if ((error = rtsx_rts5260_fill_driving(sc)))
3324 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3);
3325 RTSX_BITOP(sc, RTSX_LDO_CTL,
3331 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3);
3332 RTSX_BITOP(sc, RTSX_LDO_CTL,
3340 if (sc->rtsx_debug_mask & (RTSX_DEBUG_BASIC | RTSX_TRACE_SD_CMD))
3341 device_printf(sc->rtsx_dev, "rtsx_mmcbr_switch_vccq(%d)\n", vccq);
3353 struct rtsx_softc *sc; local
3359 sc = device_get_softc(bus);
3361 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
3362 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - hs400 is %s\n",
3365 if (sc->rtsx_ios_timing != bus_timing_uhs_sdr50)
3368 sc->rtsx_tuning_mode = true;
3370 switch (sc->rtsx_device_id) {
3373 rtsx_sd_change_tx_phase(sc, 27);
3376 rtsx_sd_change_tx_phase(sc, 20);
3379 rtsx_sd_change_tx_phase(sc, 27);
3383 rtsx_sd_change_tx_phase(sc, 29);
3388 rtsx_sd_change_tx_phase(sc, 7);
3394 rtsx_sd_tuning_rx_phase(sc, &(raw_phase_map[i]));
3401 if (sc->rtsx_debug_mask & (RTSX_DEBUG_BASIC | RTSX_DEBUG_TUNING))
3402 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX raw_phase_map[%d]: 0x%08x\n",
3406 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
3407 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX phase_map: 0x%08x\n", phase_map);
3410 final_phase = rtsx_sd_search_final_rx_phase(sc, phase_map);
3412 rtsx_sd_change_rx_phase(sc, final_phase);
3416 sc->rtsx_tuning_mode = false;
3424 struct rtsx_softc *sc; local
3426 sc = device_get_softc(bus);
3428 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
3429 device_printf(sc->rtsx_dev, "rtsx_mmcbr_retune()\n");
3438 struct rtsx_softc *sc; local
3443 sc = device_get_softc(bus);
3445 RTSX_LOCK(sc);
3446 if (sc->rtsx_req != NULL) {
3447 RTSX_UNLOCK(sc);
3450 sc->rtsx_req = req;
3453 sc->rtsx_intr_status = 0;
3454 sc->rtsx_intr_trans_ok = NULL;
3455 sc->rtsx_intr_trans_ko = rtsx_req_done;
3457 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
3458 device_printf(sc->rtsx_dev, "rtsx_mmcbr_request(CMD%u arg %#x, flags %#x, dlen %u, dflags %#x)\n",
3464 if (!ISSET(sc->rtsx_flags, RTSX_F_CARD_PRESENT)) {
3471 !ISSET(sc->rtsx_flags, RTSX_F_SDIO_SUPPORT)) {
3483 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL);
3484 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD);
3488 timeout = sc->rtsx_timeout_cmd;
3489 error = rtsx_send_req(sc, cmd);
3491 timeout = sc->rtsx_timeout_io;
3492 error = rtsx_xfer_short(sc, cmd);
3494 timeout = sc->rtsx_timeout_io;
3495 error = rtsx_xfer(sc, cmd);
3499 callout_reset(&sc->rtsx_timeout_callout, timeout * hz, rtsx_timeout, sc);
3501 rtsx_req_done(sc);
3503 RTSX_UNLOCK(sc);
3512 struct rtsx_softc *sc; local
3514 sc = device_get_softc(bus);
3516 if (sc->rtsx_inversion == 0)
3517 return (sc->rtsx_read_only);
3519 return !(sc->rtsx_read_only);
3525 struct rtsx_softc *sc; local
3527 sc = device_get_softc(bus);
3528 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
3531 RTSX_LOCK(sc);
3532 while (sc->rtsx_bus_busy)
3533 msleep(&sc->rtsx_bus_busy, &sc->rtsx_mtx, 0, "rtsxah", 0);
3534 sc->rtsx_bus_busy++;
3535 RTSX_UNLOCK(sc);
3543 struct rtsx_softc *sc; local
3545 sc = device_get_softc(bus);
3546 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
3549 RTSX_LOCK(sc);
3550 sc->rtsx_bus_busy--;
3551 wakeup(&sc->rtsx_bus_busy);
3552 RTSX_UNLOCK(sc);
3595 struct rtsx_softc *sc = device_get_softc(dev); local
3614 sc->rtsx_dev = dev;
3615 sc->rtsx_device_id = device_id;
3616 sc->rtsx_req = NULL;
3617 sc->rtsx_timeout_cmd = 1;
3618 sc->rtsx_timeout_io = 10;
3619 sc->rtsx_read_only = 0;
3620 sc->rtsx_inversion = 0;
3621 sc->rtsx_force_timing = 0;
3622 sc->rtsx_debug_mask = 0;
3623 sc->rtsx_read_count = 0;
3624 sc->rtsx_write_count = 0;
3636 sc->rtsx_inversion = 1;
3641 RTSX_LOCK_INIT(sc);
3646 &sc->rtsx_timeout_io, 0, "Request timeout for I/O commands in seconds");
3648 &sc->rtsx_timeout_cmd, 0, "Request timeout for setup commands in seconds");
3650 &sc->rtsx_read_only, 0, "Card is write protected");
3652 &sc->rtsx_inversion, 0, "Inversion of card detection and read only status");
3654 &sc->rtsx_force_timing, 0, "Force bus_timing_uhs_sdr50");
3656 &sc->rtsx_debug_mask, 0, "debugging mask, see rtsx(4)");
3658 &sc->rtsx_read_count, 0, "Count of read operations");
3660 &sc->rtsx_write_count, 0, "Count of write operations");
3662 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
3663 device_printf(dev, "We are running with inversion: %d\n", sc->rtsx_inversion);
3666 sc->rtsx_irq_res_id = 0;
3668 sc->rtsx_irq_res_id = 1;
3669 sc->rtsx_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->rtsx_irq_res_id,
3670 RF_ACTIVE | (sc->rtsx_irq_res_id != 0 ? 0 : RF_SHAREABLE));
3671 if (sc->rtsx_irq_res == NULL) {
3672 device_printf(dev, "Can't allocate IRQ resources for %d\n", sc->rtsx_irq_res_id);
3677 callout_init_mtx(&sc->rtsx_timeout_callout, &sc->rtsx_mtx, 0);
3680 if (sc->rtsx_device_id == RTSX_RTS525A)
3681 sc->rtsx_mem_res_id = PCIR_BAR(1);
3683 sc->rtsx_mem_res_id = PCIR_BAR(0);
3684 sc->rtsx_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rtsx_mem_res_id, RF_ACTIVE);
3685 if (sc->rtsx_mem_res == NULL) {
3686 device_printf(dev, "Can't allocate memory resource for %d\n", sc->rtsx_mem_res_id);
3692 sc->rtsx_irq_res_id, sc->rtsx_mem_res_id);
3694 sc->rtsx_mem_btag = rman_get_bustag(sc->rtsx_mem_res);
3695 sc->rtsx_mem_bhandle = rman_get_bushandle(sc->rtsx_mem_res);
3697 TIMEOUT_TASK_INIT(taskqueue_bus, &sc->rtsx_card_insert_task, 0,
3698 rtsx_card_task, sc);
3699 TASK_INIT(&sc->rtsx_card_remove_task, 0, rtsx_card_task, sc);
3702 error = rtsx_dma_alloc(sc);
3707 error = bus_setup_intr(dev, sc->rtsx_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
3708 NULL, rtsx_intr, sc, &sc->rtsx_irq_cookie);
3715 if (rtsx_read_cfg(sc, 0, RTSX_SDIOCFG_REG, &sdio_cfg) == 0) {
3718 sc->rtsx_flags |= RTSX_F_SDIO_SUPPORT;
3722 sc->rtsx_ccb = NULL;
3723 sc->rtsx_cam_status = 0;
3726 &sc->rtsx_cam_status, 0, "driver cam card present");
3728 if (mmc_cam_sim_alloc(dev, "rtsx_mmc", &sc->rtsx_mmc_sim) != 0) {
3735 error = rtsx_init(sc);
3749 if (rtsx_is_card_present(sc))
3750 device_printf(sc->rtsx_dev, "A card is detected\n");
3752 device_printf(sc->rtsx_dev, "No card is detected\n");
3753 rtsx_card_task(sc, 0);
3761 bus_teardown_intr(dev, sc->rtsx_irq_res, sc->rtsx_irq_cookie);
3763 bus_release_resource(dev, SYS_RES_MEMORY, sc->rtsx_mem_res_id,
3764 sc->rtsx_mem_res);
3765 rtsx_dma_free(sc);
3767 callout_drain(&sc->rtsx_timeout_callout);
3768 bus_release_resource(dev, SYS_RES_IRQ, sc->rtsx_irq_res_id,
3769 sc->rtsx_irq_res);
3771 RTSX_LOCK_DESTROY(sc);
3779 struct rtsx_softc *sc = device_get_softc(dev); local
3784 pci_get_vendor(dev), sc->rtsx_device_id);
3787 sc->rtsx_intr_enabled = 0;
3788 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled);
3791 error = bus_generic_detach(sc->rtsx_dev);
3794 sc->rtsx_mmc_dev = NULL;
3796 taskqueue_drain_timeout(taskqueue_bus, &sc->rtsx_card_insert_task);
3797 taskqueue_drain(taskqueue_bus, &sc->rtsx_card_remove_task);
3800 rtsx_dma_free(sc);
3801 if (sc->rtsx_mem_res != NULL)
3802 bus_release_resource(dev, SYS_RES_MEMORY, sc->rtsx_mem_res_id,
3803 sc->rtsx_mem_res);
3804 if (sc->rtsx_irq_cookie != NULL)
3805 bus_teardown_intr(dev, sc->rtsx_irq_res, sc->rtsx_irq_cookie);
3806 if (sc->rtsx_irq_res != NULL) {
3807 callout_drain(&sc->rtsx_timeout_callout);
3808 bus_release_resource(dev, SYS_RES_IRQ, sc->rtsx_irq_res_id,
3809 sc->rtsx_irq_res);
3812 RTSX_LOCK_DESTROY(sc);
3814 mmc_cam_sim_free(&sc->rtsx_mmc_sim);
3835 struct rtsx_softc *sc = device_get_softc(dev); local
3840 if (sc->rtsx_ccb != NULL) {
3842 sc->rtsx_ccb->mmcio.cmd.opcode, sc->rtsx_intr_status);
3845 if (sc->rtsx_req != NULL) {
3847 sc->rtsx_req->cmd->opcode, sc->rtsx_intr_status);